Remove SPI LL HAL functions that seem to be broken in latest STM32duino board package.
Replace with low level register access writes and reads.
This change also has significant performance benefits for SPI display update speed!
* Added T-DISPLAY-S3 i8080 support for more than 33 data pins (#2296)
* Modified the ESP32-S3 I8080 interface's support for data pins above 33 pins.
* Added T-DISPLAY-S3 support
* Update Setup206_LilyGo_T_Display_S3.h
* Eliminate need for TFT_DATA_PIN_OFFSET_EN in setup file
* Update TFT_eSPI_ESP32_S3.h
* Update User_Setup_Select.h
* Add new init sequence for LilyGo T Display S3
Co-authored-by: Micky <513673326@qq.com>
* Add smooth arc drawing function
Update ESP8266 architecture reference
Add pushMaskedImage() to render 16bpp images with a 1bpp mask (used for transparent PNG images plus with sprites)
New functions added using drawArc:
drawSmoothArc
drawSmoothCircle
drawSmoothRoundRect
New sqrt_fraction() added to improve smooth graphics performance on processors without a FPU (e.g. RP2040)
Faster alphaBlend() function added which retains 6bpp for green
Rename swap_coord() to transpose()
* Update TFT_eSPI.cpp
* Add arc examples
// For RP2040 processor and 8 or 16 bit parallel displays:
// The parallel interface write cycle period is derived from a division of the CPU clock
// speed so scales with the processor clock. This means that the divider ratio may need
// to be increased when overclocking. I may also need to be adjusted dependant on the
// display controller type (ILI94341, HX8357C etc). If RP2040_PIO_CLK_DIV is not defined
// the library will set default values which may not suit your display.
// The display controller data sheet will specify the minimum write cycle period. The
// controllers often work reliably for shorter periods, however if the period is too short
// the display may not initialise or graphics will become corrupted.
// PIO write cycle frequency = (CPU clock/(4 * RP2040_PIO_CLK_DIV))
//#define RP2040_PIO_CLK_DIV 1 // 32ns write cycle at 125MHz CPU clock
#define RP2040_PIO_CLK_DIV 2 // 64ns write cycle at 125MHz CPU clock
//#define RP2040_PIO_CLK_DIV 3 // 96ns write cycle at 125MHz CPU clock
