R1B2 gerbers, start+stop bits in modem driver

This commit is contained in:
Anders Nielsen 2022-10-18 11:00:00 +02:00
parent c7fb9c848d
commit dbe1feabca
21 changed files with 107932 additions and 69250 deletions

2
.gitignore vendored
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@ -8,3 +8,5 @@ hardware/_autosave-6502.kicad_sch
hardware/#auto_saved_files#
_autosave*
msbasic
*-bak
hardware/tmp

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@ -27,7 +27,7 @@ For R1 I got rid of the Padauk MCU without increasing the chip count!
3) Source the IC's - the spirit of this project is to contribute as little as possible to the global IC shortage and get used chips locally or from Ebay/AliExpress/etc.
4) Burn the ROMs. I use a TL866II Plus variant for the actual ROMs.
5) Solder away
6) For the PS/2-keyboard I use the 6522's Shift Register, PB6, and a 74xx74 flip flop. See my R1 Hardware overview at 7:46: https://youtu.be/w5cA64xof2I?t=466 This will hardware-wise be included on the next build.
6) For the PS/2-keyboard I use the 6522's Shift Register, PB6, and a 74xx74 flip flop. See my R1 Hardware overview at 7:46: https://youtu.be/w5cA64xof2I?t=466 This is now included on the board - instead of a PS/2 connector which can be harder to source I went with a USB-A-connector.
7) Enjoy!
Optional:

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@ -3,7 +3,7 @@
.feature org_per_seg
.feature c_comments
.export main, kb_rptr, PRIMM, printk, printbyte, wkey, PORTB, TIMEOUT,exitirq, printa, newline, setpulses, scrp, scwp, simpledelay, selectbaudrate, MILLISH,resetkb, clrscn,checkkeyboard, kb_buffer, MONRDKEY,CRSRPNT, t2irqreg1, MILLIS
.export I2CADDR, I2CREG, i2c_read, i2c_test, main, kb_rptr, PRIMM, printk, printbyte, wkey, PORTB, TIMEOUT,exitirq, printa, newline, setpulses, scrp, scwp, simpledelay, selectbaudrate, MILLISH,resetkb, clrscn,checkkeyboard, kb_buffer, MONRDKEY,CRSRPNT, t2irqreg1, MILLIS
;BASIC := 1 ; 1 if BASIC is enabled
;DEBUG = 1
@ -23,7 +23,7 @@ PCR = $600C ; [7:5] CB2 Control, [4] CBl Control, [3:1] CA2 Control, [0] CAl Co
IFR = $600D ; [7:0] IRQ Tl T2 CBl CB2 SR CA1 CA2
IER = $600E ; [7:0] S/C Tl T2 CBl CB2 SR CA1 CA2
PORTANHS = $600F
CTRL = $5000
CTRL = $7000
TIMEOUT = 7998 ; Should be around 2ms
@ -77,6 +77,8 @@ ABUF = movedfromzp+8 ; 8 bytes
TMP4 = movedfromzp+16
SVCSR = movedfromzp+17
;+1
I2CADDR = movedfromzp+19
I2CREG = movedfromzp+20
zp_s = $f8
kb_wptr = zp_s
@ -128,6 +130,7 @@ KCS300PH = 8 ; and 8 2400Hz pulses for a 1
TAPEVARS = movedfromzp+32
CBIT = TAPEVARS
RXBYTE = TAPEVARS+1
BITNO = TAPEVARS+1 ; Reusing
TAPEFLAGS = TAPEVARS+2
PULSES = TAPEVARS+3
NRZBYTE = TAPEVARS+4
@ -153,8 +156,8 @@ miso = %00100000
SDA = 8; PB3 bitmask
SDA_INV = $F7
SCL = 1; PB0 bitmask
SCL_INV = $FE
SCL = 16; PB4 bitmask
SCL_INV = $EF
.segment "RODATA"
;.org $8000 ; Not strictly needed with CA65 but shows correct address in listing.txt
@ -656,13 +659,23 @@ jread:
sta MONL
; inc kb_rptr
; jmp newmon
ldy #0
lda (MONL),y
jsr PRIMM
.asciiz "\nRead: "
.asciiz "\nRead:\n"
reread:
lda CRSRPNT
and #%11000000 ; keep only section bits
ora #LINESTART ;
sta CRSRPNT
ldy #0
sty kb_rptr
sty kb_wptr
lda (MONL),y
jsr printbyte
jsr checkkeyboard
beq reread
jsr PRIMM
.asciiz "\nPress F1 to enter monitor\n"
jmp eom
err:
lda CRSRPNT
@ -722,13 +735,16 @@ f2_pressed:
jmp eom
f3_pressed:
.ifdef BASIC
lda #>RAMSTART2
sta SVPH
lda #<RAMSTART2
sta SVP
.endif
jsr loadfromtape
jmp eom
f4_pressed:
.ifdef BASIC
jsr clrscn
@ -749,10 +765,11 @@ f5_pressed:
jmp run
f6_pressed:
jsr readrf24regs
jsr PRIMM
.asciiz "Read RF24 configuration!"
jsr newline
;jsr readrf24regs
;jsr PRIMM
;.asciiz "Read RF24 configuration!"
;jsr newline
jmp eom
f7_pressed:
@ -909,7 +926,7 @@ nothex:
rts
.ifdef BASIC
MONISCNTC:
sty TMP4
stx TMP3 ; X to TMP3
@ -976,6 +993,7 @@ bell:
ldx TMP3
skipcout:
rts
.endif
clrscn:
lda #0
@ -1423,6 +1441,7 @@ rts
sta kb_wptr
sta kb_rptr
sta t2irqreg1
sta kb_flags
sta T2CH
lda #1
sta CTRL
@ -1554,6 +1573,9 @@ txa ; IER AND IFR
inc ERRS ;Should never end up here...
jmp exitirq
gogmillis:
jmp gmillis
t1_irq:
bit T1CL ; Clear irq
@ -1567,20 +1589,35 @@ txa ; IER AND IFR
; SVP Save pointer low
; CBIT current bit mask
lda TAPEFLAGS ; If we just started then send a 0 bit to make the 7F leader
bpl running
and #$7F ; Remove flag
sta TAPEFLAGS
lda PULSESL ; 8 Half pulses of 1200Hz
asl ; PULSESL holds full cycles
sta PULSES
lda #3
sta T1LH
lda #$3f
sta T1LL
bne t1_irq_exit ; BRA
; Probably don't need this flag anymore
;lda TAPEFLAGS ; If we just started then send a 0 bit to make the 7F leader
;bpl running
;and #$7F ; Remove flag
;sta TAPEFLAGS
;inc BITNO
;lda PULSESL ; 8 Half pulses of 1200Hz
;asl ; PULSESL holds full cycles
;sta PULSES
;lda #3
;sta T1LH
;lda #$3f
;sta T1LL
;bne t1_irq_exit ; BRA
running:
inc BITNO
lda BITNO
cmp #13 ; This is a bit messy, could use a fix
bne notnewbyte
lda #1
sta BITNO
jmp send0
notnewbyte:
cmp #1
beq send0
cmp #10 ; Bit 10 and 11 should send a 1
bcs send1
lda CBIT
bne here ; Mask bit has not been shifted out yet
lda #1 ; Mask = LSB
@ -1596,7 +1633,7 @@ here: ; New bit
lda #1
sta T1LH
lda #$9f
bne there
bne there ; BRA
send0:
lda PULSESL ; 8 Half pulses of 1200Hz
asl ; PULSESL holds full cycles
@ -1606,6 +1643,16 @@ here: ; New bit
lda #$3f
there:
sta T1LL
lda BITNO
cmp #1
beq notdoneyet
cmp #12
beq gonextbit ; This little bit of juggling means we move on to the next byte after the stop bits
cmp #9
bcs notdoneyet
gonextbit:
clc ; Let's make sure we don't shift in a carry by mistake
asl CBIT ;Next bit
bne notdoneyet
@ -1996,6 +2043,7 @@ reversebits:
tay ; IRQ assumes y is 0.
lda #0
sta CBIT
sta BITNO
lda #135 ; Sine or cosine can be selected by odd or even leader pulses - let's make sure this number is high enough to count as a 7 "1" bits
sta PULSES ; Start with leader of x "1" pulses at TIMEOUT interval. This should be followed by #$7F to sync start bit.
@ -2036,7 +2084,6 @@ reversebits:
basicsavetotape:
.ifdef BASIC
lda #<RAMSTART2
sta SVP
lda #>RAMSTART2
@ -2105,6 +2152,7 @@ reversebits:
sta onesinarow
lda #8
sta CBIT
lda #2
sta LOADTIMEOUT
lda #$32
sta plzpnt+1
@ -2132,11 +2180,20 @@ reversebits:
sta TAPEFLAGS
noleader:
lda SVP
.ifdef BASIC
cmp #<RAMSTART2
bne noz
lda SVPH
cmp #>RAMSTART2
beq notstarted
.else
cmp #<1000
bne noz
lda SVPH
cmp #>1000
beq notstarted
.endif
noz:
lda CRSRPNT
and #%11000000 ; keep only section bits
@ -2147,10 +2204,17 @@ reversebits:
jsr printfast
sec
lda SVPH
.ifdef BASIC
sbc #>RAMSTART2
jsr printbyte
lda SVP
sbc #<RAMSTART2
.else
sbc #>1000
jsr printbyte
lda SVP
sbc #<1000
.endif
jsr printbyte
jsr PRIMM
.asciiz " bytes received"
@ -2171,7 +2235,7 @@ reversebits:
; Disable CA1 in IRQ on timeout
timeout:
jsr PRIMM
.asciiz "Finished loading.\n"
.asciiz "\nFinished loading.\n"
exituserland:
lda #2 ; Disable CA1
sta IER
@ -2322,9 +2386,31 @@ reversebits:
gtx:
jmp exitirq ; IRQ exit in ROM
checkstart:
lda #0
plp
ror
beq afternosave
jmp morebits ; Bad start bit
savebit:
php ; Save carry
lda CBIT
cmp #11 ; Check start bit
beq checkstart
cmp #2 ; Throw away parity
beq nosave
cmp #1 ; Throw away stop
beq nosave
plp
ror RXBYTE ; Shift in bit from carry
jmp afternosave
nosave:
plp
afternosave:
bit TAPEFLAGS
;Tapeflags
;$80 = nrzbit
;$40 = startbyte received
@ -2392,6 +2478,8 @@ reversebits:
;beq aprsleader
rts ; Don't want to fall through
save:
dec CBIT
bne morebits
@ -2426,7 +2514,8 @@ reversebits:
;jsr printbyte
;lda #' '
;jsr printk
lda #8
; Here we should decide if we're going for 8 or 11 bits - buts lets assume 11.
lda #11
sta CBIT
morebits:
rts
@ -2435,7 +2524,7 @@ reversebits:
lda TAPEFLAGS
ora #$60 ; Set leader flag
sta TAPEFLAGS
lda #8
lda #10 ; First time we already have the start bit
sta CBIT
rts
@ -2460,7 +2549,7 @@ NOP
bne delay
rts
/*
i2c_start: ; Let's assume i2c addr is in A and RW bit is in C
rol ; Move address to top bits and RW bit to bit0
sta outb ; Save addr + rw bit
@ -2479,7 +2568,9 @@ i2c_start: ; Let's assume i2c addr is in A and RW bit is in C
lda #SCL_INV
and PORTB
sta PORTB
inc DDRB ; Set SCL as OUTPUT LOW
lda DDRB
ora #SCL
sta DDRB ; Set SCL LOW by setting it to OUTPUT
; Fall through to send address + RW bit
; From here on we can assume OUTPUTs are LOW and INPUTS are HIGH.
@ -2491,7 +2582,9 @@ i2cbyteout:
ldx #8
i2caddrloop: ; At start of loop SDA and SCL are both OUTPUT LOW
asl outb ; Put MSB in carry
inc DDRB ; Set SCL LOW by setting it to OUTPUT
lda DDRB
ora #SCL
sta DDRB ; Set SCL LOW by setting it to OUTPUT
bcc seti2cbit0 ; If data bit was low
lda DDRB ; else set it high
and #SDA_INV
@ -2502,15 +2595,21 @@ seti2cbit0:
ora #SDA
sta DDRB
wasone:
dec DDRB ; Let SCL go HIGH by setting it to input
lda DDRB
and #SCL_INV
sta DDRB ; Set SCL HIGH by setting it to input; Let SCL go HIGH by setting it to input
dex
bne i2caddrloop
inc DDRB ; Set SCL low after last bit
lda DDRB
ora #SCL
sta DDRB ; Set SCL LOW by setting it to OUTPUT ; Set SCL low after last bit
lda DDRB ; Set SDA to INPUT
and #SDA_INV
sta DDRB
dec DDRB ; SCL high
lda DDRB
and #SCL_INV
sta DDRB ; Set SCL HIGH by setting it to input
; NOP here?
lda PORTB ; Check ACK bit
clc
@ -2518,67 +2617,104 @@ seti2cbit0:
bne nack
sec ; Set carry to indicate ACK
nack:
inc DDRB ; SCL low
lda DDRB
ora #SCL
sta DDRB ; Set SCL LOW by setting it to OUTPUT
rts
i2cbytein: ; Assume SCL is LOW
lda DDRB ; Set SDA to input
and #SDA_INV
sta DDRB
lda #0
sta inb
ldx #8
byteinloop:
clc ; Clearing here for more even cycle
dec DDRB ; SCL high
; NOP?
lda DDRB
and #SCL_INV
sta DDRB ; Set SCL HIGH by setting it to input
nop
lda PORTB
and #SDA
beq got0
sec
got0:
rol inb ; Shift carry into input byte
inc DDRB ; SCL low
lda DDRB
ora #SCL
sta DDRB ; Set SCL LOW by setting it to OUTPUT
dex
bne byteinloop
lda DDRB ; Send ACK
ora #SDA
sta DDRB
dec DDRB ; SCL high
nop ; Probably can't just toggle
inc DDRB ; Set clock low
lda DDRB ; Set SDA to input (release it) - maybe not necessary
lda DDRB ; Send NACK == SDA high (because we're ony fetching single bytes)
and #SDA_INV
sta DDRB
lda DDRB
and #SCL_INV
sta DDRB ; Set SCL HIGH by setting it to input
lda DDRB
ora #SCL
sta DDRB ; Set SCL LOW by setting it to OUTPUT
rts ; Input byte in inb
i2c_stop:
lda DDRB ; SDA low
ora #SDA
sta DDRB
dec DDRB ; SCL high
lda DDRB
and #SCL_INV
sta DDRB ; Set SCL HIGH by setting it to input
nop
nop
lda DDRB ; Set SDA high after SCL == Stop condition.
and #SDA_INV
sta DDRB
rts
i2c_test:
lda #$77 ; Address $77 = BMP180 address
;lda #$77 ; Address $77 = BMP180 address
lda I2CADDR
clc ; Write
jsr i2c_start
; Fail check here. C == 1 == ACK
bcc failed
lda #$D0 ; BMP180 register $D0 == chipID == $55
;lda #$D0 ; BMP180 register $D0 == chipID == $55
lda I2CREG ; VGA screen EDID usually has address $50
sta outb
jsr i2cbyteout
lda #$77 ; Address
;lda #$77 ; Address
lda I2CADDR
sec ; Read
jsr i2c_start
jsr i2cbytein
jsr i2c_stop
lda inb
sec
rts
failed:
lda #0
rts
*/
i2c_read:
lda I2CADDR
clc ; We "write" the address we want to read from
jsr i2c_start
bcc readfail
lda #0
sta outb
jsr i2cbyteout
jsr i2c_stop
lda I2CADDR
sec ; Now we read the register data
jsr i2c_start
jsr i2cbytein
jsr i2c_stop
lda inb
readfail:
rts
rubout:
ldy #0

15
crom.s
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@ -1,10 +1,25 @@
; CROM source
.segment "CROM"
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$18,$66,$66,$18,$62,$3c,$06,$0c,$30,$00,$00,$00,$00,$00,$00,$3c,$18,$3c,$3c,$06,$7e,$3c,$7e,$3c,$3c,$00,$00,$0e,$00,$70,$3c,$3c,$18,$7c,$3c,$78,$7e,$7e,$3c,$66,$3c,$1e,$66,$60,$63,$66,$3c,$7c,$3c,$7c,$3c,$7e,$66,$66,$63,$66,$66,$7e,$3c,$00,$3c,$00,$00,$3c,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$0e,$08,$70,$00,$ff
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$18,$66,$66,$18,$62,$3c,$06,$0c,$30,$00,$00,$00,$00,$00,$00,$3c,$18,$3c,$3c,$06,$7e,$3c,$7e,$3c,$3c,$00,$00,$0e,$00,$70,$3c,$3c,$18,$7c,$3c,$78,$7e,$7e,$3c,$66,$3c,$1e,$66,$60,$63,$66,$3c,$7c,$3c,$7c,$3c,$7e,$66,$66,$63,$66,$66,$7e,$3c,$00,$3c,$00,$00,$3c,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$0e,$08,$70,$00,$ff
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$18,$66,$66,$3e,$66,$66,$0c,$18,$18,$66,$18,$00,$00,$00,$03,$66,$18,$66,$66,$0e,$60,$66,$66,$66,$66,$00,$00,$18,$00,$18,$66,$66,$3c,$66,$66,$6c,$60,$60,$66,$66,$18,$0c,$6c,$60,$77,$76,$66,$66,$66,$66,$66,$18,$66,$66,$63,$66,$66,$06,$30,$60,$0c,$18,$00,$66,$00,$60,$00,$06,$00,$0e,$00,$60,$18,$06,$60,$38,$00,$00,$00,$00,$00,$00,$00,$18,$00,$00,$00,$00,$00,$00,$18,$18,$18,$00,$ff
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$18,$66,$66,$3e,$66,$66,$0c,$18,$18,$66,$18,$00,$00,$00,$03,$66,$18,$66,$66,$0e,$60,$66,$66,$66,$66,$00,$00,$18,$00,$18,$66,$66,$3c,$66,$66,$6c,$60,$60,$66,$66,$18,$0c,$6c,$60,$77,$76,$66,$66,$66,$66,$66,$18,$66,$66,$63,$66,$66,$06,$30,$60,$0c,$18,$00,$66,$00,$60,$00,$06,$00,$0e,$00,$60,$18,$06,$60,$38,$00,$00,$00,$00,$00,$00,$00,$18,$00,$00,$00,$00,$00,$00,$18,$18,$18,$00,$ff
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$18,$66,$ff,$60,$0c,$3c,$18,$30,$0c,$3c,$18,$00,$00,$00,$06,$6e,$38,$06,$06,$1e,$7c,$60,$0c,$66,$66,$18,$18,$30,$7e,$0c,$06,$6e,$66,$66,$60,$66,$60,$60,$60,$66,$18,$0c,$78,$60,$7f,$7e,$66,$66,$66,$66,$60,$18,$66,$66,$63,$3c,$66,$0c,$30,$30,$0c,$3c,$00,$6e,$3c,$60,$3c,$06,$3c,$18,$3e,$60,$00,$00,$60,$18,$66,$7c,$3c,$7c,$3e,$7c,$3e,$7e,$66,$66,$63,$66,$66,$7e,$18,$18,$18,$00,$ff
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$18,$66,$ff,$60,$0c,$3c,$18,$30,$0c,$3c,$18,$00,$00,$00,$06,$6e,$38,$06,$06,$1e,$7c,$60,$0c,$66,$66,$18,$18,$30,$7e,$0c,$06,$6e,$66,$66,$60,$66,$60,$60,$60,$66,$18,$0c,$78,$60,$7f,$7e,$66,$66,$66,$66,$60,$18,$66,$66,$63,$3c,$66,$0c,$30,$30,$0c,$3c,$00,$6e,$3c,$60,$3c,$06,$3c,$18,$3e,$60,$00,$00,$60,$18,$66,$7c,$3c,$7c,$3e,$7c,$3e,$7e,$66,$66,$63,$66,$66,$7e,$18,$18,$18,$00,$ff
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$18,$00,$66,$3c,$18,$38,$00,$30,$0c,$ff,$7e,$00,$7e,$00,$0c,$76,$18,$0c,$1c,$66,$06,$7c,$18,$3c,$3e,$00,$00,$60,$00,$06,$0c,$6e,$7e,$7c,$60,$66,$78,$78,$6e,$7e,$18,$0c,$70,$60,$6b,$7e,$66,$7c,$66,$7c,$3c,$18,$66,$66,$6b,$18,$3c,$18,$30,$18,$0c,$7e,$00,$6e,$06,$7c,$60,$3e,$66,$3e,$66,$7c,$38,$06,$6c,$18,$7f,$66,$66,$66,$66,$66,$60,$18,$66,$66,$6b,$3c,$66,$0c,$70,$18,$0e,$3b,$ff
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$18,$00,$66,$3c,$18,$38,$00,$30,$0c,$ff,$7e,$00,$7e,$00,$0c,$76,$18,$0c,$1c,$66,$06,$7c,$18,$3c,$3e,$00,$00,$60,$00,$06,$0c,$6e,$7e,$7c,$60,$66,$78,$78,$6e,$7e,$18,$0c,$70,$60,$6b,$7e,$66,$7c,$66,$7c,$3c,$18,$66,$66,$6b,$18,$3c,$18,$30,$18,$0c,$7e,$00,$6e,$06,$7c,$60,$3e,$66,$3e,$66,$7c,$38,$06,$6c,$18,$7f,$66,$66,$66,$66,$66,$60,$18,$66,$66,$6b,$3c,$66,$0c,$70,$18,$0e,$3b,$ff
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138852
hardware/6502.kicad_pcb Executable file → Normal file

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@ -45,7 +45,7 @@
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
"min_clearance": 0.254
}
},
"diff_pair_dimensions": [
@ -55,7 +55,9 @@
"width": 0.0
}
],
"drc_exclusions": [],
"drc_exclusions": [
"malformed_courtyard|78960923|111955923|4412226e-d975-40a2-921f-502ff4129a95|00000000-0000-0000-0000-000000000000"
],
"meta": {
"filename": "board_design_settings.json",
"version": 2
@ -64,7 +66,7 @@
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",

2939
hardware/6502.kicad_sch Executable file → Normal file

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0
hardware/fp-info-cache Executable file → Normal file
View File

2040
hardware/ram-vga.kicad_sch Executable file → Normal file

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@ -1,3 +1,3 @@
(sym_lib_table
(lib (name 6502-rescue)(type Legacy)(uri ${KIPRJMOD}/6502-rescue.lib)(options "")(descr ""))
(lib (name "6502-rescue")(type "Legacy")(uri "${KIPRJMOD}/6502-rescue.lib")(options "")(descr ""))
)

View File

@ -1,5 +1,6 @@
.feature string_escapes ; Allow c-style string escapes when using ca65
.feature c_comments
;PRIMM = $FFC8 ; Userland can use ROM subroutines if we tell them where they are. Check listing.txt for current subroutine addresses
;.require "abn6502rom.s"
.import kb_rptr: zeropage, scrp: zeropage, scwp: zeropage, CRSRPNT: zeropage, MILLIS: zeropage, MILLISH: zeropage
@ -30,6 +31,7 @@ inc kb_rptr
jsr printa
userland:
lda #$0A
jsr printk
jsr PRIMM
@ -62,6 +64,25 @@ cOhtwotest:
lda #<main
jsr printbyte
lda #$7f
sta I2CREG+1
lda I2CADDR
jsr printbyte
lda #':'
jsr printk
dumpi2c:
inc CRSRPNT
bne l77
inc CRSRPNT+1
l77:
jsr i2c_test
;rol
jsr printbyte
inc I2CREG
dec I2CREG+1
bne dumpi2c
; waitforkey:
; jsr MONRDKEY
; bcc waitforkey
@ -69,7 +90,7 @@ cOhtwotest:
; beq done
; jsr printa
; jmp waitforkey
; done:
done:
brk
;jmp main