mirror of
https://github.com/espressif/arduino-esp32
synced 2024-09-21 02:18:29 +00:00
143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp32-hal.h"
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#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM
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#include "soc/efuse_reg.h"
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#include "esp_heap_caps.h"
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#include "esp_system.h"
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#include "esp_psram.h"
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#include "esp_private/esp_psram_extram.h"
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#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
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#include "esp32/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/cache.h"
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#else
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#error Target CONFIG_IDF_TARGET is not supported
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#endif
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static volatile bool spiramDetected = false;
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static volatile bool spiramFailed = false;
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//allows user to bypass SPI RAM test routine
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__attribute__((weak)) bool testSPIRAM(void) {
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return esp_psram_extram_test();
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}
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bool psramInit() {
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if (spiramDetected) {
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return true;
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}
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#ifndef CONFIG_SPIRAM_BOOT_INIT
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if (spiramFailed) {
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return false;
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}
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#if CONFIG_IDF_TARGET_ESP32
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE);
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uint32_t pkg_ver = chip_ver & 0x7;
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if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
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spiramFailed = true;
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log_w("PSRAM not supported!");
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return false;
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}
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#elif CONFIG_IDF_TARGET_ESP32S2
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extern void esp_config_data_cache_mode(void);
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esp_config_data_cache_mode();
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Cache_Enable_DCache(0);
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#endif
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if (esp_psram_init() != ESP_OK) {
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spiramFailed = true;
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log_w("PSRAM init failed!");
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#if CONFIG_IDF_TARGET_ESP32
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if (pkg_ver != EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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pinMatrixOutDetach(16, false, false);
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pinMatrixOutDetach(17, false, false);
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}
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#endif
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return false;
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}
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//testSPIRAM() allows user to bypass SPI RAM test routine
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if (!testSPIRAM()) {
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spiramFailed = true;
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log_e("PSRAM test failed!");
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return false;
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}
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if (esp_psram_extram_add_to_heap_allocator() != ESP_OK) {
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spiramFailed = true;
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log_e("PSRAM could not be added to the heap!");
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return false;
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}
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#if CONFIG_SPIRAM_USE_MALLOC && !CONFIG_ARDUINO_ISR_IRAM
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heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
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#endif
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#endif /* CONFIG_SPIRAM_BOOT_INIT */
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log_i("PSRAM enabled");
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spiramDetected = true;
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return true;
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}
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bool ARDUINO_ISR_ATTR psramFound() {
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return spiramDetected;
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}
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void ARDUINO_ISR_ATTR *ps_malloc(size_t size) {
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if (!spiramDetected) {
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return NULL;
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}
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return heap_caps_malloc(size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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}
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void ARDUINO_ISR_ATTR *ps_calloc(size_t n, size_t size) {
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if (!spiramDetected) {
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return NULL;
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}
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return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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}
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void ARDUINO_ISR_ATTR *ps_realloc(void *ptr, size_t size) {
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if (!spiramDetected) {
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return NULL;
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}
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return heap_caps_realloc(ptr, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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}
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#else
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bool psramInit() {
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return false;
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}
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bool ARDUINO_ISR_ATTR psramFound() {
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return false;
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}
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void ARDUINO_ISR_ATTR *ps_malloc(size_t size) {
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return NULL;
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}
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void ARDUINO_ISR_ATTR *ps_calloc(size_t n, size_t size) {
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return NULL;
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}
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void ARDUINO_ISR_ATTR *ps_realloc(void *ptr, size_t size) {
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return NULL;
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}
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#endif
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