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Update IDF libs

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me-no-dev 2016-12-02 14:50:43 +02:00
parent e77ec634a9
commit ee36407b43
66 changed files with 2295 additions and 296 deletions
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4
platform.txt
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@ -13,7 +13,7 @@ compiler.warning_flags.all=-Wall -Wextra
compiler.path={runtime.tools.xtensa-esp32-elf-gcc.path}/bin/
compiler.sdk.path={runtime.platform.path}/tools/sdk
compiler.cpreprocessor.flags=-DESP_PLATFORM -DMBEDTLS_CONFIG_FILE='"mbedtls/esp_config.h"' -DHAVE_CONFIG_H "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/bt" "-I{compiler.sdk.path}/include/driver" "-I{compiler.sdk.path}/include/esp32" "-I{compiler.sdk.path}/include/freertos" "-I{compiler.sdk.path}/include/log" "-I{compiler.sdk.path}/include/vfs" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/nvs_flash" "-I{compiler.sdk.path}/include/spi_flash" "-I{compiler.sdk.path}/include/openssl" "-I{compiler.sdk.path}/include/tcpip_adapter" "-I{compiler.sdk.path}/include/xtensa-debug-module" "-I{compiler.sdk.path}/include/wpa_supplicant" "-I{compiler.sdk.path}/include/expat" "-I{compiler.sdk.path}/include/json" "-I{compiler.sdk.path}/include/mbedtls" "-I{compiler.sdk.path}/include/nghttp" "-I{compiler.sdk.path}/include/lwip"
compiler.cpreprocessor.flags=-DESP_PLATFORM -DMBEDTLS_CONFIG_FILE='"mbedtls/esp_config.h"' -DHAVE_CONFIG_H "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/bt" "-I{compiler.sdk.path}/include/driver" "-I{compiler.sdk.path}/include/esp32" "-I{compiler.sdk.path}/include/ethernet" "-I{compiler.sdk.path}/include/freertos" "-I{compiler.sdk.path}/include/log" "-I{compiler.sdk.path}/include/vfs" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/nvs_flash" "-I{compiler.sdk.path}/include/spi_flash" "-I{compiler.sdk.path}/include/openssl" "-I{compiler.sdk.path}/include/tcpip_adapter" "-I{compiler.sdk.path}/include/xtensa-debug-module" "-I{compiler.sdk.path}/include/wpa_supplicant" "-I{compiler.sdk.path}/include/expat" "-I{compiler.sdk.path}/include/json" "-I{compiler.sdk.path}/include/mbedtls" "-I{compiler.sdk.path}/include/nghttp" "-I{compiler.sdk.path}/include/lwip"
compiler.c.cmd=xtensa-esp32-elf-gcc
compiler.c.flags=-c {compiler.warning_flags} -Os -g3 -Wpointer-arith -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -ffunction-sections -fdata-sections -mlongcalls -nostdlib -MMD -std=gnu99 -fstrict-volatile-bitfields
@ -26,7 +26,7 @@ compiler.S.flags=-c -g3 -x assembler-with-cpp -MMD -mlongcalls
compiler.c.elf.cmd=xtensa-esp32-elf-gcc
compiler.c.elf.flags="-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" -nostdlib -T esp32_out.ld -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static -Wl,--undefined=uxTopUsedPriority
compiler.c.elf.libs=-lbt -lbtdm_app -lc -lcoexist -lcore -ldriver -lesp32 -lexpat -lfreertos -lg -lhal -ljson -llog -llwip -lm -lmbedtls -lnet80211 -lnewlib -lnghttp -lnvs_flash -lopenssl -lphy -lpp -lrtc -lsmartconfig -lspi_flash -ltcpip_adapter -lvfs -lwpa -lwpa_supplicant -lwps -lxtensa-debug-module
compiler.c.elf.libs=-lapp_update -lbt -lbtdm_app -lc -lcoexist -lcore -ldriver -lesp32 -lethernet -lexpat -lfreertos -lg -lhal -ljson -llog -llwip -lm -lmbedtls -lnet80211 -lnewlib -lnghttp -lnvs_flash -lopenssl -lphy -lpp -lrtc -lsmartconfig -lspi_flash -ltcpip_adapter -lvfs -lwpa -lwpa2 -lwpa_supplicant -lwps -lxtensa-debug-module
compiler.as.cmd=xtensa-esp32-elf-as

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tools/sdk/bin/bootloader.bin
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3
tools/sdk/include/config/sdkconfig.h
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@ -30,6 +30,7 @@
#define CONFIG_MBEDTLS_MPI_USE_INTERRUPT 1
#define CONFIG_MAIN_TASK_STACK_SIZE 4096
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
#define CONFIG_BTC_TASK_STACK_SIZE 2048
#define CONFIG_LOG_DEFAULT_LEVEL 1
#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
#define CONFIG_PYTHON "python"
@ -54,11 +55,11 @@
#define CONFIG_LWIP_SO_REUSE 1
#define CONFIG_BT_ENABLED 1
#define CONFIG_MONITOR_BAUD 115200
#define CONFIG_MBEDTLS_HARDWARE_SHA 1
#define CONFIG_FREERTOS_CORETIMER_0 1
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
#define CONFIG_OPTIMIZATION_LEVEL_DEBUG 1
#define CONFIG_ESP32_PHY_AUTO_INIT 0
#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE 32
#define CONFIG_ESPTOOLPY_BAUD_921600B 1
#define CONFIG_APP_OFFSET 0x10000

349
tools/sdk/include/driver/driver/timer.h Normal file
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@ -0,0 +1,349 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_TIMER_H_
#define _DRIVER_TIMER_H_
#include "esp_err.h"
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/timer_group_reg.h"
#include "soc/timer_group_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define TIMER_BASE_CLK (APB_CLK_FREQ)
/**
* @brief Selects a Timer-Group out of 2 available groups
*/
typedef enum {
TIMER_GROUP_0 = 0, /*!<Hw timer group 0*/
TIMER_GROUP_1 = 1, /*!<Hw timer group 1*/
TIMER_GROUP_MAX,
} timer_group_t;
/**
* @brief Select a hardware timer from timer groups
*/
typedef enum {
TIMER_0 = 0, /*!<Select timer0 of GROUPx*/
TIMER_1 = 1, /*!<Select timer1 of GROUPx*/
TIMER_MAX,
} timer_idx_t;
/**
* @brief Decides the direction of counter
*/
typedef enum {
TIMER_COUNT_DOWN = 0, /*!< Descending Count from cnt.high|cnt.low*/
TIMER_COUNT_UP = 1, /*!< Ascending Count from Zero*/
TIMER_COUNT_MAX
} timer_count_dir_t;
/**
* @brief Decides whether timer is on or paused
*/
typedef enum {
TIMER_PAUSE = 0, /*!<Pause timer counter*/
TIMER_START = 1, /*!<Start timer counter*/
} timer_start_t;
/**
* @brief Decides whether to enable alarm mode
*/
typedef enum {
TIMER_ALARM_DIS = 0, /*!< Disable timer alarm*/
TIMER_ALARM_EN = 1, /*!< Enable timer alarm*/
TIMER_ALARM_MAX
} timer_alarm_t;
/**
* @brief Select interrupt type if running in alarm mode.
*/
typedef enum {
TIMER_INTR_LEVEL = 0, /*!< Interrupt mode: level mode*/
//TIMER_INTR_EDGE = 1, /*!< Interrupt mode: edge mode, Not supported Now*/
TIMER_INTR_MAX
} timer_intr_mode_t;
/**
* @brief Select if Alarm needs to be loaded by software or automatically reload by hardware.
*/
typedef enum {
TIMER_AUTORELOAD_DIS = 0, /*!< Disable auto-reload: hardware will not load counter value after an alarm event*/
TIMER_AUTORELOAD_EN = 1, /*!< Enable auto-reload: hardware will load counter value after an alarm event*/
TIMER_AUTORELOAD_MAX,
} timer_autoreload_t;
/**
* @brief timer configure struct
*/
typedef struct {
bool alarm_en; /*!< Timer alarm enable */
bool counter_en; /*!< Counter enable */
timer_count_dir_t counter_dir; /*!< Counter direction */
timer_intr_mode_t intr_type; /*!< Interrupt mode */
bool auto_reload; /*!< Timer auto-reload */
uint16_t divider; /*!< Counter clock divider*/
} timer_config_t;
/**
* @brief Read the counter value of hardware timer.
*
* @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param timer_val Pointer to accept timer counter value.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t* timer_val);
/**
* @brief Read the counter value of hardware timer, in unit of a given scale.
*
* @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param time Pointer, type of double*, to accept timer counter value, in seconds.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_num, double* time);
/**
* @brief Set counter value to hardware timer.
*
* @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param load_val Counter value to write to the hardware timer.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_set_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t load_val);
/**
* @brief Start the counter of hardware timer.
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_start(timer_group_t group_num, timer_idx_t timer_num);
/**
* @brief Pause the counter of hardware timer.
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_pause(timer_group_t group_num, timer_idx_t timer_num);
/**
* @brief Set counting mode for hardware timer.
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param counter_dir Counting direction of timer, count-up or count-down
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_set_counter_mode(timer_group_t group_num, timer_idx_t timer_num, timer_count_dir_t counter_dir);
/**
* @brief Enable or disable counter reload function when alarm event occurs.
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param reload Counter reload mode.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_set_auto_reload(timer_group_t group_num, timer_idx_t timer_num, timer_autoreload_t reload);
/**
* @brief Set hardware timer source clock divider. Timer groups clock are divider from APB clock.
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param divider Timer clock divider value.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint16_t divider);
/**
* @brief Set timer alarm value.
*
* @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param alarm_value A 64-bit value to set the alarm value.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_set_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_value);
/**
* @brief Get timer alarm value.
*
* @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param alarm_value Pointer of A 64-bit value to accept the alarm value.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_get_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t* alarm_value);
/**
* @brief Get timer alarm value.
*
* @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param alarm_en To enable or disable timer alarm function.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_alarm_t alarm_en);
/**
* @brief register Timer interrupt handler, the handler is an ISR.
* The handler will be attached to the same CPU core that this function is running on.
* @note
* Users should know that which CPU is running and then pick a INUM that is not used by system.
* We can find the information of INUM and interrupt level in soc.h.
*
* @param group_num Timer group number
* @param timer_num Timer index of timer group
* @param timer_intr_num TIMER interrupt number, check the info in soc.h, and please see the core-isa.h for more details
* @param intr_type Timer interrupt type
* @param fn Interrupt handler function.
* @note
* Code inside the handler function can only call functions in IRAM, so cannot call other timer APIs.
* Use direct register access to access timers from inside the ISR.
*
* @param arg Parameter for handler function
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Function pointer error.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num, int timer_intr_num, timer_intr_mode_t intr_type, void (*fn)(void*), void * arg);
/** @brief Initializes and configure the timer.
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param config Pointer to timer initialization parameters.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, timer_config_t* config);
/** @brief Get timer configure value.
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
* @param config Pointer of struct to accept timer parameters.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_get_config(timer_group_t group_num, timer_idx_t timer_num, timer_config_t *config);
/** @brief Enable timer group interrupt, by enable mask
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param en_mask Timer interrupt enable mask.
* Use TIMG_T0_INT_ENA_M to enable t0 interrupt
* Use TIMG_T1_INT_ENA_M to enable t1 interrupt
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_group_intr_enable(timer_group_t group_num, uint32_t en_mask);
/** @brief Disable timer group interrupt, by disable mask
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param disable_mask Timer interrupt disable mask.
* Use TIMG_T0_INT_ENA_M to disable t0 interrupt
* Use TIMG_T1_INT_ENA_M to disable t1 interrupt
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_group_intr_disable(timer_group_t group_num, uint32_t disable_mask);
/** @brief Enable timer interrupt
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num);
/** @brief Disable timer interrupt
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param timer_num Timer index.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num);
#ifdef __cplusplus
}
#endif
#endif /* _TIMER_H_ */

5
tools/sdk/include/esp32/esp_event.h
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@ -45,6 +45,11 @@ typedef enum {
SYSTEM_EVENT_AP_STADISCONNECTED, /**< a station disconnected from ESP32 soft-AP */
SYSTEM_EVENT_AP_PROBEREQRECVED, /**< Receive probe request packet in soft-AP interface */
SYSTEM_EVENT_AP_STA_GOT_IP6, /**< ESP32 station or ap interface v6IP addr is preferred */
SYSTEM_EVENT_ETH_START, /**< ESP32 ethernet start */
SYSTEM_EVENT_ETH_STOP, /**< ESP32 ethernet stop */
SYSTEM_EVENT_ETH_CONNECTED, /**< ESP32 ethernet phy link up */
SYSTEM_EVENT_ETH_DISCONNECTED, /**< ESP32 ethernet phy link down */
SYSTEM_EVENT_ETH_GOT_IP, /**< ESP32 ethernet got IP from connected AP */
SYSTEM_EVENT_MAX
} system_event_id_t;

37
tools/sdk/include/esp32/esp_interface.h Normal file
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@ -0,0 +1,37 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_INTERFACE_H__
#define __ESP_INTERFACE_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ESP_IF_WIFI_STA = 0, /**< ESP32 station interface */
ESP_IF_WIFI_AP, /**< ESP32 soft-AP interface */
ESP_IF_ETH, /**< ESP32 ethernet interface */
ESP_IF_MAX
} esp_interface_t;
#ifdef __cplusplus
}
#endif
#endif /* __ESP_INTERFACE_TYPES_H__ */

5
tools/sdk/include/esp32/esp_wifi.h
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@ -87,6 +87,7 @@ extern "C" {
#define ESP_ERR_WIFI_SSID (ESP_ERR_WIFI_BASE + 9) /*!< SSID is invalid */
#define ESP_ERR_WIFI_PASSWORD (ESP_ERR_WIFI_BASE + 10) /*!< Passord is invalid */
#define ESP_ERR_WIFI_TIMEOUT (ESP_ERR_WIFI_BASE + 11) /*!< Timeout error */
#define ESP_ERR_WIFI_WAKE_FAIL (ESP_ERR_WIFI_BASE + 12) /*!< WiFi is in sleep state(RF closed) and wakeup fail */
/**
* @brief WiFi stack configuration parameters passed to esp_wifi_init call.
@ -327,6 +328,8 @@ esp_err_t esp_wifi_sta_get_ap_info(wifi_ap_record_t *ap_info);
/**
* @brief Set current power save type
*
* @attention Default power save type is WIFI_PS_NONE.
*
* @param type power save type
*
* @return ESP_ERR_WIFI_NOT_SUPPORT: not supported yet
@ -336,6 +339,8 @@ esp_err_t esp_wifi_set_ps(wifi_ps_type_t type);
/**
* @brief Get current power save type
*
* @attention Default power save type is WIFI_PS_NONE.
*
* @param[out] type: store current power save type
*
* @return ESP_ERR_WIFI_NOT_SUPPORT: not supported yet

12
tools/sdk/include/esp32/esp_wifi_types.h
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@ -21,6 +21,7 @@
#include "rom/queue.h"
#include "esp_err.h"
#include "esp_wifi_types.h"
#include "esp_interface.h"
#ifdef __cplusplus
extern "C" {
@ -34,11 +35,10 @@ typedef enum {
WIFI_MODE_MAX
} wifi_mode_t;
typedef enum {
WIFI_IF_STA = 0, /**< ESP32 station interface */
WIFI_IF_AP, /**< ESP32 soft-AP interface */
WIFI_IF_MAX
} wifi_interface_t;
typedef esp_interface_t wifi_interface_t;
#define WIFI_IF_STA ESP_IF_WIFI_STA
#define WIFI_IF_AP ESP_IF_WIFI_AP
typedef enum {
WIFI_COUNTRY_CN = 0, /**< country China, channel range [1, 14] */
@ -114,8 +114,6 @@ typedef struct {
typedef enum {
WIFI_PS_NONE, /**< No power save */
WIFI_PS_MODEM, /**< Modem power save */
WIFI_PS_LIGHT, /**< Light power save */
WIFI_PS_MAC, /**< MAC power save */
} wifi_ps_type_t;
#define WIFI_PROTOCOL_11B 1

166
tools/sdk/include/esp32/esp_wpa2.h Normal file
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@ -0,0 +1,166 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ESP_WPA2_H
#define ESP_WPA2_H
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable wpa2 enterprise authentication.
*
* @attention wpa2 enterprise authentication can only be used when ESP32 station is enabled.
* wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
*
* @return ESP_ERR_WIFI_OK: succeed.
* ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_enable(void);
/**
* @brief Disable wpa2 enterprise authentication.
*
* @attention wpa2 enterprise authentication can only be used when ESP32 station is enabled.
* wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
*
* @return ESP_ERR_WIFI_OK: succeed.
*/
esp_err_t esp_wifi_sta_wpa2_ent_disable(void);
/**
* @brief Set username for PEAP/TTLS method.
*
* @attention The API only passes the parameter username to the global pointer variable in wpa2 enterprise module.
*
* @param username: point to address where stores the username;
* len: length of username, limited to 1~127
*
* @return ESP_ERR_WIFI_OK: succeed
* ESP_ERR_WIFI_ARG: fail(len <= 0 or len >= 128)
* ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_username(unsigned char *username, int len);
/**
* @brief Clear username for PEAP/TTLS method.
*/
void esp_wifi_sta_wpa2_ent_clear_username(void);
/**
* @brief Set password for PEAP/TTLS method..
*
* @attention The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
*
* @param password: point to address where stores the password;
* len: length of password(len > 0)
*
* @return ESP_ERR_WIFI_OK: succeed
* ESP_ERR_WIFI_ARG: fail(len <= 0)
* ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_password(unsigned char *password, int len);
/**
* @brief Clear password for PEAP/TTLS method..
*/
void esp_wifi_sta_wpa2_ent_clear_password(void);
/**
* @brief Set new password for MSCHAPv2 method..
*
* @attention The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
* The new password is used to substitute the old password when eap-mschapv2 failure request message with error code ERROR_PASSWD_EXPIRED is received.
*
* @param password: point to address where stores the password;
* len: length of password
*
* @return ESP_ERR_WIFI_OK: succeed
* ESP_ERR_WIFI_ARG: fail(len <= 0)
* ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_new_password(unsigned char *password, int len);
/**
* @brief Clear new password for MSCHAPv2 method..
*/
void esp_wifi_sta_wpa2_ent_clear_new_password(void);
/**
* @brief Set CA certificate for PEAP/TTLS method.
*
* @attention The API only passes the parameter ca_cert to the global pointer variable in wpa2 enterprise module.
* The ca_cert should be zero terminated.
*
* @param ca_cert: point to address where stores the CA certificate;
* len: length of ca_cert
*
* @return ESP_ERR_WIFI_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_ca_cert(unsigned char *ca_cert, int len);
/**
* @brief Clear CA certificate for PEAP/TTLS method.
*/
void esp_wifi_sta_wpa2_ent_clear_ca_cert(void);
/**
* @brief Set client certificate and key.
*
* @attention The API only passes the parameter client_cert, private_key and private_key_passwd to the global pointer variable in wpa2 enterprise module.
* The client_cert, private_key and private_key_passwd should be zero terminated.
*
* @param client_cert: point to address where stores the client certificate;
* client_cert_len: length of client certificate;
* private_key: point to address where stores the private key;
* private_key_len: length of private key, limited to 1~2048;
* private_key_password: point to address where stores the private key password;
* private_key_password_len: length of private key password;
*
* @return ESP_ERR_WIFI_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_cert_key(unsigned char *client_cert, int client_cert_len, unsigned char *private_key, int private_key_len, unsigned char *private_key_passwd, int private_key_passwd_len);
/**
* @brief Clear client certificate and key.
*/
void esp_wifi_sta_wpa2_ent_clear_cert_key(void);
/**
* @brief Set wpa2 enterprise certs time check(disable or not).
*
* @param true: disable wpa2 enterprise certs time check
* false: enable wpa2 enterprise certs time check
*
* @return ESP_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_disable_time_check(bool disable);
/**
* @brief Get wpa2 enterprise certs time check(disable or not).
*
* @param disable: store disable value
*
* @return ESP_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_get_disable_time_check(bool *disable);
#ifdef __cplusplus
}
#endif
#endif

329
tools/sdk/include/esp32/hwcrypto/sha.h
View File

@ -1,246 +1,203 @@
/*
* ESP32 hardware accelerated SHA1/256/512 implementation
* based on mbedTLS FIPS-197 compliant version.
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP_SHA_H_
#define _ESP_SHA_H_
#include "rom/sha.h"
#include "esp_types.h"
/** @brief Low-level support functions for the hardware SHA engine
*
* @note If you're looking for a SHA API to use, try mbedtls component
* mbedtls/shaXX.h. That API supports hardware acceleration.
*
* The API in this header provides some building blocks for implementing a
* full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha().
*
* Some technical details about the hardware SHA engine:
*
* - SHA accelerator engine calculates one digest at a time, per SHA
* algorithm type. It initialises and maintains the digest state
* internally. It is possible to read out an in-progress SHA digest
* state, but it is not possible to restore a SHA digest state
* into the engine.
*
* - The memory block SHA_TEXT_BASE is shared between all SHA digest
* engines, so all engines must be idle before this memory block is
* modified.
*
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief SHA-1 context structure
*/
typedef struct {
/* both types defined in rom/sha.h */
SHA_CTX context;
enum SHA_TYPE context_type;
} esp_sha_context;
/* Defined in rom/sha.h */
typedef enum SHA_TYPE esp_sha_type;
/**
* \brief Lock access to SHA hardware unit
/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine
*
* SHA hardware unit can only be used by one
* consumer at a time.
* @note For more versatile SHA calculations, where data doesn't need
* to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The
* hardware-accelerated mbedTLS implementation is also faster when
* hashing large amounts of data.
*
* esp_sha_xxx API calls automatically manage locking & unlocking of
* hardware, this function is only needed if you want to call
* ets_sha_xxx functions directly.
*/
void esp_sha_acquire_hardware( void );
/**
* \brief Unlock access to SHA hardware unit
* @note It is not necessary to lock any SHA hardware before calling
* this function, thread safety is managed internally.
*
* esp_sha_xxx API calls automatically manage locking & unlocking of
* hardware, this function is only needed if you want to call
* ets_sha_xxx functions directly.
*/
void esp_sha_release_hardware( void );
/**
* \brief Initialize SHA-1 context
* @note If a TLS connection is open then this function may block
* indefinitely waiting for a SHA engine to become available. Use the
* mbedTLS SHA API to avoid this problem.
*
* \param ctx SHA-1 context to be initialized
*/
void esp_sha1_init( esp_sha_context *ctx );
/**
* \brief Clear SHA-1 context
* @param sha_type SHA algorithm to use.
*
* \param ctx SHA-1 context to be cleared
*/
void esp_sha1_free( esp_sha_context *ctx );
/**
* \brief Clone (the state of) a SHA-1 context
* @param input Input data buffer.
*
* \param dst The destination context
* \param src The context to be cloned
*/
void esp_sha1_clone( esp_sha_context *dst, const esp_sha_context *src );
/**
* \brief SHA-1 context setup
* @param ilen Length of input data in bytes.
*
* \param ctx context to be initialized
* @param output Buffer for output SHA digest. Output is 20 bytes for
* sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for
* sha_type SHA2_384, 64 bytes for sha_type SHA2_512.
*/
void esp_sha1_start( esp_sha_context *ctx );
void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output);
/**
* \brief SHA-1 process buffer
/* @brief Begin to execute a single SHA block operation
*
* \param ctx SHA-1 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void esp_sha1_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen );
/**
* \brief SHA-1 final digest
* @note This is a piece of a SHA algorithm, rather than an entire SHA
* algorithm.
*
* \param ctx SHA-1 context
* \param output SHA-1 checksum result
*/
void esp_sha1_finish( esp_sha_context *ctx, unsigned char output[20] );
/**
* \brief Calculate SHA-1 of input buffer
* @note Call esp_sha_try_lock_engine() before calling this
* function. Do not call esp_sha_lock_memory_block() beforehand, this
* is done inside the function.
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param output SHA-1 checksum result
*/
void esp_sha1( const unsigned char *input, size_t ilen, unsigned char output[20] );
/**
* \brief SHA-256 context structure
*/
/**
* \brief Initialize SHA-256 context
* @param sha_type SHA algorithm to use.
*
* \param ctx SHA-256 context to be initialized
*/
void esp_sha256_init( esp_sha_context *ctx );
/**
* \brief Clear SHA-256 context
* @param data_block Pointer to block of data. Block size is
* determined by algorithm (SHA1/SHA2_256 = 64 bytes,
* SHA2_384/SHA2_512 = 128 bytes)
*
* \param ctx SHA-256 context to be cleared
*/
void esp_sha256_free( esp_sha_context *ctx );
/**
* \brief Clone (the state of) a SHA-256 context
* @param is_first_block If this parameter is true, the SHA state will
* be initialised (with the initial state of the given SHA algorithm)
* before the block is calculated. If false, the existing state of the
* SHA engine will be used.
*
* \param dst The destination context
* \param src The context to be cloned
* @return As a performance optimisation, this function returns before
* the SHA block operation is complete. Both this function and
* esp_sha_read_state() will automatically wait for any previous
* operation to complete before they begin. If using the SHA registers
* directly in another way, call esp_sha_wait_idle() after calling this
* function but before accessing the SHA registers.
*/
void esp_sha256_clone( esp_sha_context *dst, const esp_sha_context *src );
void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block);
/**
* \brief SHA-256 context setup
/** @brief Read out the current state of the SHA digest loaded in the engine.
*
* \param ctx context to be initialized
* \param is224 0 = use SHA256, 1 = use SHA224
*/
void esp_sha256_start( esp_sha_context *ctx, int is224 );
/**
* \brief SHA-256 process buffer
* @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm.
*
* \param ctx SHA-256 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void esp_sha256_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen );
/**
* \brief SHA-256 final digest
* @note Call esp_sha_try_lock_engine() before calling this
* function. Do not call esp_sha_lock_memory_block() beforehand, this
* is done inside the function.
*
* \param ctx SHA-256 context
* \param output SHA-224/256 checksum result
*/
void esp_sha256_finish( esp_sha_context *ctx, unsigned char output[32] );
/**
* \brief Calculate SHA-256 of input buffer
* If the SHA suffix padding block has been executed already, the
* value that is read is the SHA digest (in big endian
* format). Otherwise, the value that is read is an interim SHA state.
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param output SHA-224/256 checksum result
* \param is224 0 = use SHA256, 1 = use SHA224
*/
void esp_sha256( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 );
//
/**
* \brief SHA-512 context structure
*/
/**
* \brief Initialize SHA-512 context
* @note If sha_type is SHA2_384, only 48 bytes of state will be read.
* This is enough for the final SHA2_384 digest, but if you want the
* interim SHA-384 state (to continue digesting) then pass SHA2_512 instead.
*
* @param sha_type SHA algorithm in use.
*
* @param state Pointer to a memory buffer to hold the SHA state. Size
* is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512).
*
* \param ctx SHA-512 context to be initialized
*/
void esp_sha512_init( esp_sha_context *ctx );
void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state);
/**
* \brief Clear SHA-512 context
* @brief Obtain exclusive access to a particular SHA engine
*
* \param ctx SHA-512 context to be cleared
* @param sha_type Type of SHA engine to use.
*
* Blocks until engine is available. Note: Can block indefinitely
* while a TLS connection is open, suggest using
* esp_sha_try_lock_engine() and failing over to software SHA.
*/
void esp_sha512_free( esp_sha_context *ctx );
void esp_sha_lock_engine(esp_sha_type sha_type);
/**
* \brief Clone (the state of) a SHA-512 context
* @brief Try and obtain exclusive access to a particular SHA engine
*
* \param dst The destination context
* \param src The context to be cloned
* @param sha_type Type of SHA engine to use.
*
* @return Returns true if the SHA engine is locked for exclusive
* use. Call esp_sha_unlock_sha_engine() when done. Returns false if
* the SHA engine is already in use, caller should use software SHA
* algorithm for this digest.
*/
void esp_sha512_clone( esp_sha_context *dst, const esp_sha_context *src );
bool esp_sha_try_lock_engine(esp_sha_type sha_type);
/**
* \brief SHA-512 context setup
* @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine()
*
* \param ctx context to be initialized
* \param is384 0 = use SHA512, 1 = use SHA384
* @param sha_type Type of engine to release.
*/
void esp_sha512_start( esp_sha_context *ctx, int is384 );
void esp_sha_unlock_engine(esp_sha_type sha_type);
/**
* \brief SHA-512 process buffer
* @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE
*
* \param ctx SHA-512 context
* \param input buffer holding the data
* \param ilen length of the input data
* This memory block is shared across all the SHA algorithm types.
*
* Caller should have already locked a SHA engine before calling this function.
*
* Note that it is possible to obtain exclusive access to the memory block even
* while it is in use by the SHA engine. Caller should use esp_sha_wait_idle()
* to ensure the SHA engine is not reading from the memory block in hardware.
*
* @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally.
*
* Call esp_sha_unlock_memory_block() when done.
*/
void esp_sha512_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen );
void esp_sha_lock_memory_block(void);
/**
* \brief SHA-512 final digest
* @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE
*
* \param ctx SHA-512 context
* \param output SHA-384/512 checksum result
*/
void esp_sha512_finish( esp_sha_context *ctx, unsigned char output[64] );
/**
* \brief Calculate SHA-512 of input buffer.
* Caller should have already locked a SHA engine before calling this function.
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param output SHA-384/512 checksum result
* \param is384 0 = use SHA512, 1 = use SHA384
* Call following esp_sha_lock_memory_block().
*/
void esp_sha512( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 );
void esp_sha_unlock_memory_block(void);
//
/** @brief Wait for the SHA engine to finish any current operation
*
* @note This function does not ensure exclusive access to any SHA
* engine. Caller should use esp_sha_try_lock_engine() and
* esp_sha_lock_memory_block() as required.
*
* @note Functions declared in this header file wait for SHA engine
* completion automatically, so you don't need to use this API for
* these. However if accessing SHA registers directly, you will need
* to call this before accessing SHA registers if using the
* esp_sha_block() function.
*
* @note This function busy-waits, so wastes CPU resources.
* Best to delay calling until you are about to need it.
*
*/
void esp_sha_wait_idle(void);
#ifdef __cplusplus
}

9
tools/sdk/include/esp32/rom/sha.h
View File

@ -1,9 +1,10 @@
/*
ROM functions for hardware SHA support.
It is not recommended to use these functions directly,
use the wrapper functions in hwcrypto/sha.h instead.
It is not recommended to use these functions directly. If using
them from esp-idf then use the esp_sha_lock_engine() and
esp_sha_lock_memory_block() functions in hwcrypto/sha.h to ensure
exclusive access.
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
@ -38,6 +39,8 @@ enum SHA_TYPE {
SHA2_256,
SHA2_384,
SHA2_512,
SHA_INVALID = -1,
};

9
tools/sdk/include/esp32/rom/spi_flash.h
View File

@ -384,7 +384,8 @@ SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t blo
SpiFlashOpResult SPIEraseChip(void);
/**
* @brief Erase a block of flash.
* @brief Erase a 32KB block of flash
* Uses SPI flash command 52h.
* Please do not call this function in SDK.
*
* @param uint32_t block_num : Which block to erase.
@ -411,6 +412,12 @@ SpiFlashOpResult SPIEraseSector(uint32_t sector_num);
* @brief Erase some sectors.
* Please do not call this function in SDK.
*
* @note If calling this function, first set
* g_rom_flashchip.block_size = 32768; or call SPIParamCfg()
* with appropriate parameters. This is due to a ROM bug, the
* block erase command in use is a 32KB erase but after reset
* the block_size field is incorrectly set to 65536.
*
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
*
* @param uint32_t area_len : Length to erase, should be sector aligned.

10
tools/sdk/include/esp32/soc/dport_reg.h
View File

@ -94,6 +94,16 @@
#define DPORT_PERI_RST_EN_V 0xFFFFFFFF
#define DPORT_PERI_RST_EN_S 0
/* The following bits apply to DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG
*/
#define DPORT_PERI_EN_AES (1<<0)
#define DPORT_PERI_EN_SHA (1<<1)
#define DPORT_PERI_EN_RSA (1<<2)
/* NB: Secure boot reset will hold SHA & AES in reset */
#define DPORT_PERI_EN_SECUREBOOT (1<<3)
/* NB: Digital signature reset will hold AES & RSA in reset */
#define DPORT_PERI_EN_DIGITAL_SIGNATURE (1<<4)
#define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024)
/* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */

101
tools/sdk/include/esp32/soc/emac_ex_reg.h Normal file
View File

@ -0,0 +1,101 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _EMAC_EX_H_
#define _EMAC_EX_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define REG_EMAC_EX_BASE (DR_REG_EMAC_BASE + 0x800)
#define EMAC_EX_CLKOUT_CONF_REG (REG_EMAC_EX_BASE + 0x0000)
#define EMAC_EX_CLK_OUT_DLY_NUM 0x00000003
#define EMAC_EX_CLK_OUT_DLY_NUM_S 8
#define EMAC_EX_CLK_OUT_H_DIV_NUM 0x0000000F
#define EMAC_EX_CLK_OUT_H_DIV_NUM_S 4
#define EMAC_EX_CLK_OUT_DIV_NUM 0x0000000F
#define EMAC_EX_CLK_OUT_DIV_NUM_S 0
#define EMAC_EX_OSCCLK_CONF_REG (REG_EMAC_EX_BASE + 0x0004)
#define EMAC_EX_OSC_CLK_SEL (BIT(24))
#define EMAC_EX_OSC_CLK_SEL_S 24
#define EMAC_EX_OSC_H_DIV_NUM_100M 0x0000003F
#define EMAC_EX_OSC_H_DIV_NUM_100M_S 18
#define EMAC_EX_OSC_DIV_NUM_100M 0x0000003F
#define EMAC_EX_OSC_DIV_NUM_100M_S 12
#define EMAC_EX_OSC_H_DIV_NUM_10M 0x0000003F
#define EMAC_EX_OSC_H_DIV_NUM_10M_S 6
#define EMAC_EX_OSC_DIV_NUM_10M 0x0000003F
#define EMAC_EX_OSC_DIV_NUM_10M_S 0
#define EMAC_EX_CLK_CTRL_REG (REG_EMAC_EX_BASE + 0x0008)
#define EMAC_EX_CLK_EN (BIT(5))
#define EMAC_EX_CLK_EN_S 5
#define EMAC_EX_MII_CLK_RX_EN (BIT(4))
#define EMAC_EX_MII_CLK_RX_EN_S 4
#define EMAC_EX_MII_CLK_TX_EN (BIT(3))
#define EMAC_EX_MII_CLK_TX_EN_S 3
#define EMAC_EX_RX_125_CLK_EN (BIT(2))
#define EMAC_EX_RX_125_CLK_EN_S 2
#define EMAC_EX_INT_OSC_EN (BIT(1))
#define EMAC_EX_INT_OSC_EN_S 1
#define EMAC_EX_EXT_OSC_EN (BIT(0))
#define EMAC_EX_EXT_OSC_EN_S 0
#define EMAC_EX_PHYINF_CONF_REG (REG_EMAC_EX_BASE + 0x000c)
#define EMAC_EX_TX_ERR_OUT_EN (BIT(20))
#define EMAC_EX_TX_ERR_OUT_EN_S 20
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC (BIT(19))
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_S 19
#define EMAC_EX_PMT_CTRL_EN (BIT(18))
#define EMAC_EX_PMT_CTRL_EN_S 18
#define EMAC_EX_SBD_CLK_GATING_EN (BIT(17))
#define EMAC_EX_SBD_CLK_GATING_EN_S 17
#define EMAC_EX_SS_MODE (BIT(16))
#define EMAC_EX_SS_MODE_S 16
#define EMAC_EX_PHY_INTF_SEL 0x00000007
#define EMAC_EX_PHY_INTF_SEL_S 13
#define EMAC_EX_REVMII_PHY_ADDR 0x0000001F
#define EMAC_EX_REVMII_PHY_ADDR_S 8
#define EMAC_EX_CORE_PHY_ADDR 0x0000001F
#define EMAC_EX_CORE_PHY_ADDR_S 3
#define EMAC_EX_SBD_FLOWCTRL (BIT(2))
#define EMAC_EX_SBD_FLOWCTRL_S 2
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL (BIT(1))
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_S 1
#define EMAC_EX_INT_REVMII_RX_CLK_SEL (BIT(0))
#define EMAC_EX_INT_REVMII_RX_CLK_SEL_S 0
#define EMAC_EX_PHY_INTF_RMII 4
#define EMAC_EX_EMAC_PD_SEL_REG (REG_EMAC_EX_BASE + 0x0010)
#define EMAC_EX_RAM_PD_EN 0x00000003
#define EMAC_EX_RAM_PD_EN_S 0
#define EMAC_EX_DATE_REG (REG_EMAC_EX_BASE + 0x00fc)
#define EMAC_EX_DATE 0xFFFFFFFF
#define EMAC_EX_DATE_S 0
#define EMAC_EX_DATE_VERSION 0x16042200
#define EMAC_CLK_EN_REG 0x3ff000cc
#define EMAC_CLK_EN (BIT(14))
#ifdef __cplusplus
}
#endif
#endif

714
tools/sdk/include/esp32/soc/emac_reg_v2.h Normal file
View File

@ -0,0 +1,714 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _EMAC_H_
#define _EMAC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define REG_EMAC_BASE DR_REG_EMAC_BASE
#define EMAC_DMABUSMODE_REG (REG_EMAC_BASE + 0x0000)
#define EMAC_DMAREBINCRBURST (BIT(31))
#define EMAC_DMAREBINCRBURST_S 31
#define EMAC_DMACHANNELPRIOWT 0x00000003
#define EMAC_DMACHANNELPRIOWT_S 28
#define EMAC_DMATXRXPRIO (BIT(27))
#define EMAC_DMATXRXPRIO_S 27
#define EMAC_DMAMIXEDBURST (BIT(26))
#define EMAC_DMAMIXEDBURST_S 26
#define EMAC_DMAADDRALIBEA (BIT(25))
#define EMAC_DMAADDRALIBEA_S 25
#define EMAC_PBLX8_MODE (BIT(24))
#define EMAC_PBLX8_MODE_S 24
#define EMAC_USE_SEP_PBL (BIT(23))
#define EMAC_USE_SEP_PBL_S 23
#define EMAC_RX_DMA_PBL 0x0000003F
#define EMAC_RX_DMA_PBL_S 17
#define EMAC_FIXED_BURST (BIT(16))
#define EMAC_FIXED_BURST_S 16
#define EMAC_PRI_RATIO 0x00000003
#define EMAC_PRI_RATIO_S 14
#define EMAC_PROG_BURST_LEN 0x0000003F
#define EMAC_PROG_BURST_LEN_S 8
#define EMAC_ALT_DESC_SIZE (BIT(7))
#define EMAC_ALT_DESC_SIZE_S 7
#define EMAC_DESC_SKIP_LEN 0x0000001F
#define EMAC_DESC_SKIP_LEN_S 2
#define EMAC_DMA_ARB_SCH (BIT(1))
#define EMAC_DMA_ARB_SCH_S 1
#define EMAC_SW_RST (BIT(0))
#define EMAC_SW_RST_S 0
#define EMAC_DMATXPOLLDEMAND_REG (REG_EMAC_BASE + 0x0004)
#define EMAC_TRANS_POLL_DEMAND 0xFFFFFFFF
#define EMAC_TRANS_POLL_DEMAND_S 0
#define EMAC_DMARXPOLLDEMAND_REG (REG_EMAC_BASE + 0x0008)
#define EMAC_RECV_POLL_DEMAND 0xFFFFFFFF
#define EMAC_RECV_POLL_DEMAND_S 0
#define EMAC_DMARXBASEADDR_REG (REG_EMAC_BASE + 0x000C)
#define EMAC_START_RECV_LIST 0xFFFFFFFF
#define EMAC_START_RECV_LIST_S 0
#define EMAC_DMATXBASEADDR_REG (REG_EMAC_BASE + 0x0010)
#define EMAC_START_TRANS_LIST 0xFFFFFFFF
#define EMAC_START_TRANS_LIST_S 0
#define EMAC_DMASTATUS_REG (REG_EMAC_BASE + 0x0014)
#define EMAC_GMAC_LPI_INT (BIT(30))
#define EMAC_GMAC_LPI_INT_S 30
#define EMAC_TS_TRI_INT (BIT(29))
#define EMAC_TS_TRI_INT_S 29
#define EMAC_GMAC_PMT_INT (BIT(28))
#define EMAC_GMAC_PMT_INT_S 28
#define EMAC_GMAC_MMC_INT (BIT(27))
#define EMAC_GMAC_MMC_INT_S 27
#define EMAC_GMAC_LINE_INF_INT (BIT(26))
#define EMAC_GMAC_LINE_INF_INT_S 26
#define EMAC_ERROR_BITS 0x00000007
#define EMAC_ERROR_BITS_S 23
#define EMAC_TRANS_PROC_STATE 0x00000007
#define EMAC_TRANS_PROC_STATE_S 20
#define EMAC_RECV_PROC_STATE 0x00000007
#define EMAC_RECV_PROC_STATE_S 17
#define EMAC_NORM_INT_SUMM (BIT(16))
#define EMAC_NORM_INT_SUMM_S 16
#define EMAC_ABN_INT_SUMM (BIT(15))
#define EMAC_ABN_INT_SUMM_S 15
#define EMAC_EARLY_RECV_INT (BIT(14))
#define EMAC_EARLY_RECV_INT_S 14
#define EMAC_FATAL_BUS_ERR_INT (BIT(13))
#define EMAC_FATAL_BUS_ERR_INT_S 13
#define EMAC_EARLY_TRANS_INT (BIT(10))
#define EMAC_EARLY_TRANS_INT_S 10
#define EMAC_RECV_WDT_TO (BIT(9))
#define EMAC_RECV_WDT_TO_S 9
#define EMAC_RECV_PROC_STOP (BIT(8))
#define EMAC_RECV_PROC_STOP_S 8
#define EMAC_RECV_BUF_UNAVAIL (BIT(7))
#define EMAC_RECV_BUF_UNAVAIL_S 7
#define EMAC_RECV_INT (BIT(6))
#define EMAC_RECV_INT_S 6
#define EMAC_TRANS_UNDFLOW (BIT(5))
#define EMAC_TRANS_UNDFLOW_S 5
#define EMAC_RECV_OVFLOW (BIT(4))
#define EMAC_RECV_OVFLOW_S 4
#define EMAC_TRANS_JABBER_TO (BIT(3))
#define EMAC_TRANS_JABBER_TO_S 3
#define EMAC_TRANS_BUF_UNAVAIL (BIT(2))
#define EMAC_TRANS_BUF_UNAVAIL_S 2
#define EMAC_TRANS_PROC_STOP (BIT(1))
#define EMAC_TRANS_PROC_STOP_S 1
#define EMAC_TRANS_INT (BIT(0))
#define EMAC_TRANS_INT_S 0
#define EMAC_DMAOPERATION_MODE_REG (REG_EMAC_BASE + 0x0018)
#define EMAC_DIS_DROP_TCPIP_CHKSUM_ERR_FRAM (BIT(26))
#define EMAC_DIS_DROP_TCPIP_CHKSUM_ERR_FRAM_S 26
#define EMAC_RECV_STORE_FORWARD (BIT(25))
#define EMAC_RECV_STORE_FORWARD_S 25
#define EMAC_DIS_FLUSH_RECV_FRAMES (BIT(24))
#define EMAC_DIS_FLUSH_RECV_FRAMES_S 24
#define EMAC_MSB_THRESHOLD_ACTIVATING_FLOW_CONTROL (BIT(23))
#define EMAC_MSB_THRESHOLD_ACTIVATING_FLOW_CONTROL_S 23
#define EMAC_MSB_THRESHOLD_DEACTIVATING_FLOW_CONTROL (BIT(22))
#define EMAC_MSB_THRESHOLD_DEACTIVATING_FLOW_CONTROL_S 22
#define EMAC_TRANSMIT_STORE_FORWARD (BIT(21))
#define EMAC_TRANSMIT_STORE_FORWARD_S 21
#define EMAC_FLUSH_TRANSMIT_FIFO (BIT(20))
#define EMAC_FLUSH_TRANSMIT_FIFO_S 20
#define EMAC_TRANSMIT_THRESHOLD_CONTROL 0x00000007
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_S 14
#define EMAC_START_STOP_TRANSMISSION_COMMAND (BIT(13))
#define EMAC_START_STOP_TRANSMISSION_COMMAND_S 13
#define EMAC_THRESHOLD_DEACTIVATING_FLOW_CONTROL 0x00000003
#define EMAC_THRESHOLD_DEACTIVATING_FLOW_CONTROL_S 11
#define EMAC_THRESHOLD_ACTIVATING_FLOW_CONTROL 0x00000003
#define EMAC_THRESHOLD_ACTIVATING_FLOW_CONTROL_S 9
#define EMAC_ENABLE_HW_FLOW_CONTROL (BIT(8))
#define EMAC_ENABLE_HW_FLOW_CONTROL_S 8
#define EMAC_FORWARD_ERROR_FRAMES (BIT(7))
#define EMAC_FORWARD_ERROR_FRAMES_S 7
#define EMAC_FORWARD_UNDERSIZED_GOOD_FRAMES (BIT(6))
#define EMAC_FORWARD_UNDERSIZED_GOOD_FRAMES_S 6
#define EMAC_DROP_GIANT_FRAMES (BIT(5))
#define EMAC_DROP_GIANT_FRAMES_S 5
#define EMAC_RECEIVE_THRESHOLD_CONTROL 0x00000003
#define EMAC_RECEIVE_THRESHOLD_CONTROL_S 3
#define EMAC_OPERATE_SECOND_FRAME (BIT(2))
#define EMAC_OPERATE_SECOND_FRAME_S 2
#define EMAC_START_STOP_RECEIVE (BIT(1))
#define EMAC_START_STOP_RECEIVE_S 1
#define EMAC_DMAINTERRUPT_EN_REG (REG_EMAC_BASE + 0x001C)
#define EMAC_NORMAL_INTERRUPT_SUMMARY_ENABLE (BIT(16))
#define EMAC_NORMAL_INTERRUPT_SUMMARY_ENABLE_S 16
#define EMAC_ABNORMAL_INTERRUPT_SUMMARY_ENABLE (BIT(15))
#define EMAC_ABNORMAL_INTERRUPT_SUMMARY_ENABLE_S 15
#define EMAC_EARLY_RECEIVE_INTERRUPT_ENABLE (BIT(14))
#define EMAC_EARLY_RECEIVE_INTERRUPT_ENABLE_S 14
#define EMAC_FATAL_BUS_ERROR_ENABLE (BIT(13))
#define EMAC_FATAL_BUS_ERROR_ENABLE_S 13
#define EMAC_EARLY_TRANSMIT_INTERRUPT_ENABLE (BIT(10))
#define EMAC_EARLY_TRANSMIT_INTERRUPT_ENABLE_S 10
#define EMAC_RECEIVE_WATCHDOG_TIMEOUT_ENABLE (BIT(9))
#define EMAC_RECEIVE_WATCHDOG_TIMEOUT_ENABLE_S 9
#define EMAC_RECEIVE_STOPPED_ENABLE (BIT(8))
#define EMAC_RECEIVE_STOPPED_ENABLE_S 8
#define EMAC_RECEIVE_BUFFER_UNAVAILABLE_ENABLE (BIT(7))
#define EMAC_RECEIVE_BUFFER_UNAVAILABLE_ENABLE_S 7
#define EMAC_RECEIVE_INTERRUPT_ENABLE (BIT(6))
#define EMAC_RECEIVE_INTERRUPT_ENABLE_S 6
#define EMAC_UNDERFLOW_INTERRUPT_ENABLE (BIT(5))
#define EMAC_UNDERFLOW_INTERRUPT_ENABLE_S 5
#define EMAC_OVERFLOW_INTERRUPT_ENABLE (BIT(4))
#define EMAC_OVERFLOW_INTERRUPT_ENABLE_S 4
#define EMAC_TRANSMIT_JABBER_TIMEOUT_ENABLE (BIT(3))
#define EMAC_TRANSMIT_JABBER_TIMEOUT_ENABLE_S 3
#define EMAC_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE (BIT(2))
#define EMAC_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE_S 2
#define EMAC_TRANSMIT_STOPPED_ENABLE (BIT(1))
#define EMAC_TRANSMIT_STOPPED_ENABLE_S 1
#define EMAC_TRANSMIT_INTERRUPT_ENABLE (BIT(0))
#define EMAC_TRANSMIT_INTERRUPT_ENABLE_S 0
#define EMAC_DMAMISSEDFR_REG (REG_EMAC_BASE + 0x0020)
#define EMAC_OVERFLOW_BIT_FIFO_OVERFLOW_COUNTER (BIT(28))
#define EMAC_OVERFLOW_BIT_FIFO_OVERFLOW_COUNTER_S 28
#define EMAC_OVERFLOW_FRAME_COUNTER 0x000007FF
#define EMAC_OVERFLOW_FRAME_COUNTER_S 17
#define EMAC_OVERFLOW_BIT_MISSED_FRAME_COUNTER (BIT(16))
#define EMAC_OVERFLOW_BIT_MISSED_FRAME_COUNTER_S 16
#define EMAC_MISSED_FRAME_COUNTER 0x0000FFFF
#define EMAC_MISSED_FRAME_COUNTER_S 0
#define EMAC_DMARECEIVE_INTERRUPT_WATCHDOG_TIMER_REG (REG_EMAC_BASE + 0x0024)
#define EMAC_RI_WATCHDOG_TIMER_COUNT 0x000000FF
#define EMAC_RI_WATCHDOG_TIMER_COUNT_S 0
#define EMAC_DMATXCURRDESC_REG (REG_EMAC_BASE + 0x0048)
#define EMAC_HOST_TRANSMIT_DESCRIPTOR_ADDRESS_POINTER 0xFFFFFFFF
#define EMAC_HOST_TRANSMIT_DESCRIPTOR_ADDRESS_POINTER_S 0
#define EMAC_DMARXCURRDESC_REG (REG_EMAC_BASE + 0x004C)
#define EMAC_HOST_RECEIVE_DESCRIPTOR_ADDRESS_POINTER 0xFFFFFFFF
#define EMAC_HOST_RECEIVE_DESCRIPTOR_ADDRESS_POINTER_S 0
#define EMAC_DMATXCURRADDR_BUF_REG (REG_EMAC_BASE + 0x0050)
#define EMAC_HOST_TRANSMIT_BUFFER_ADDRESS_POINTER 0xFFFFFFFF
#define EMAC_HOST_TRANSMIT_BUFFER_ADDRESS_POINTER_S 0
#define EMAC_DMARXCURRADDR_BUF_REG (REG_EMAC_BASE + 0x0054)
#define EMAC_HOST_RECEIVE_BUFFER_ADDRESS_POINTER 0xFFFFFFFF
#define EMAC_HOST_RECEIVE_BUFFER_ADDRESS_POINTER_S 0
#define EMAC_DMAHWFEATURE_REG (REG_EMAC_BASE + 0x0058)
#define EMAC_SELECTED_PHY_INTERFACE 0x00000007
#define EMAC_SELECTED_PHY_INTERFACE_S 28
#define EMAC_SOURCE_ADDRESS_VLAN_INSERTION (BIT(27))
#define EMAC_SOURCE_ADDRESS_VLAN_INSERTION_S 27
#define EMAC_FLEXIBLE_PULSE_PER_SECOND_OUTPUT (BIT(26))
#define EMAC_FLEXIBLE_PULSE_PER_SECOND_OUTPUT_S 26
#define EMAC_TIMESTAMPING_INTERNAL_SYSTEM_TIME (BIT(25))
#define EMAC_TIMESTAMPING_INTERNAL_SYSTEM_TIME_S 25
#define EMAC_ENHANCED_DESCRIPTOR (BIT(24))
#define EMAC_ENHANCED_DESCRIPTOR_S 24
#define EMAC_NUMBER_ADDITIONAL_TX_CHANNELS 0x00000003
#define EMAC_NUMBER_ADDITIONAL_TX_CHANNELS_S 22
#define EMAC_NUMBER_ADDITIONAL_RX_CHANNELS 0x00000003
#define EMAC_NUMBER_ADDITIONAL_RX_CHANNELS_S 20
#define EMAC_RXFIFOSIZE (BIT(19))
#define EMAC_RXFIFOSIZE_S 19
#define EMAC_IP_CHECKSUM_OFFLOAD_TYPE2 (BIT(18))
#define EMAC_IP_CHECKSUM_OFFLOAD_TYPE2_S 18
#define EMAC_IP_CHECKSUM_OFFLOAD_TYPE1 (BIT(17))
#define EMAC_IP_CHECKSUM_OFFLOAD_TYPE1_S 17
#define EMAC_CHECKSUM_OFFLOAD_TX (BIT(16))
#define EMAC_CHECKSUM_OFFLOAD_TX_S 16
#define EMAC_AV_FEATURE_SEL (BIT(15))
#define EMAC_AV_FEATURE_SEL_S 15
#define EMAC_EEE_SEL (BIT(14))
#define EMAC_EEE_SEL_S 14
#define EMAC_TSVER2_SEL (BIT(13))
#define EMAC_TSVER2_SEL_S 13
#define EMAC_TSVER1_SEL (BIT(12))
#define EMAC_TSVER1_SEL_S 12
#define EMAC_MMC_SEL (BIT(11))
#define EMAC_MMC_SEL_S 11
#define EMAC_MGK_SEL (BIT(10))
#define EMAC_MGK_SEL_S 10
#define EMAC_RWK_SEL (BIT(9))
#define EMAC_RWK_SEL_S 9
#define EMAC_SMA_SEL (BIT(8))
#define EMAC_SMA_SEL_S 8
#define EMAC_L3L4FLTR_EN (BIT(7))
#define EMAC_L3L4FLTR_EN_S 7
#define EMAC_PCS_SEL (BIT(6))
#define EMAC_PCS_SEL_S 6
#define EMAC_ADDMACADR_SEL (BIT(5))
#define EMAC_ADDMACADR_SEL_S 5
#define EMAC_HASH_SEL (BIT(4))
#define EMAC_HASH_SEL_S 4
#define EMAC_EXTHASH_EN (BIT(3))
#define EMAC_EXTHASH_EN_S 3
#define EMAC_HD_SEL (BIT(2))
#define EMAC_HD_SEL_S 2
#define EMAC_GMII_SEL (BIT(1))
#define EMAC_GMII_SEL_S 1
#define EMAC_MII_SEL (BIT(0))
#define EMAC_MII_SEL_S 0
#define EMAC_DMASLOTFNCTRLSTS_REG (REG_EMAC_BASE + 0x0130)
#define EMAC_REFERENCE_SLOT_NUMBER 0x0000000F
#define EMAC_REFERENCE_SLOT_NUMBER_S 16
#define EMAC_ADVANCE_SLOT_CHECK (BIT(1))
#define EMAC_ADVANCE_SLOT_CHECK_S 1
#define EMAC_ENABLE_SLOT_COMPARISON (BIT(0))
#define EMAC_ENABLE_SLOT_COMPARISON_S 0
#define EMAC_DMACHANNELCTRL_REG (REG_EMAC_BASE + 0x0160)
#define EMAC_AVERAGE_BITS_PER_SLOT_INTERRUPT_ENABLE (BIT(17))
#define EMAC_AVERAGE_BITS_PER_SLOT_INTERRUPT_ENABLE_S 17
#define EMAC_SLOT_COUNT 0x00000007
#define EMAC_SLOT_COUNT_S 4
#define EMAC_CREDIT_CONTROL (BIT(1))
#define EMAC_CREDIT_CONTROL_S 1
#define EMAC_CREDIT_BASED_SHAPER_DISABLE (BIT(0))
#define EMAC_CREDIT_BASED_SHAPER_DISABLE_S 0
#define EMAC_DMACHANNELAVSTS_REG (REG_EMAC_BASE + 0x0064)
#define EMAC_ABS_UPDATED (BIT(17))
#define EMAC_ABS_UPDATED_S 17
#define EMAC_AVERAGE_BITS_PER_SLOT 0x0001FFFF
#define EMAC_AVERAGE_BITS_PER_SLOT_S 0
#define EMAC_DMAIDLESLOPECREDIT_REG (REG_EMAC_BASE + 0x0068)
#define EMAC_IDLESLOPECREDIT 0x00003FFF
#define EMAC_IDLESLOPECREDIT_S 0
#define EMAC_DMASENDSLOPECREDIT_REG (REG_EMAC_BASE + 0x006C)
#define EMAC_SENDSLOPECREDIT 0x00003FFF
#define EMAC_SENDSLOPECREDIT_S 0
#define EMAC_DMAHIGHCREDIT_REG (REG_EMAC_BASE + 0x0070)
#define EMAC_HICREDIT 0x1FFFFFFF
#define EMAC_HICREDIT_S 0
#define EMAC_DMALOCREDIT_REG (REG_EMAC_BASE + 0x0074)
#define EMAC_LOCREDIT 0x1FFFFFFF
#define EMAC_LOCREDIT_S 0
#define EMAC_GMACCONFIG_REG (REG_EMAC_BASE + 0x1000)
#define EMAC_SOURCE_ADDRESS_INSERTION_REPLACEMENT_CONTROL 0x00000007
#define EMAC_SOURCE_ADDRESS_INSERTION_REPLACEMENT_CONTROL_S 28
#define EMAC_AS_SUPPORT_2K_PACKETS (BIT(27))
#define EMAC_AS_SUPPORT_2K_PACKETS_S 27
#define EMAC_SMII_FORCE_TRANSMIT_ERROR (BIT(26))
#define EMAC_SMII_FORCE_TRANSMIT_ERROR_S 26
#define EMAC_CRC_STRIPPING_TYPE_FRAMES (BIT(25))
#define EMAC_CRC_STRIPPING_TYPE_FRAMES_S 25
#define EMAC_TRANSMIT_CONFIGURATION (BIT(24))
#define EMAC_TRANSMIT_CONFIGURATION_S 24
#define EMAC_GMACWATCHDOG (BIT(23))
#define EMAC_GMACWATCHDOG_S 23
#define EMAC_GMACJABBER (BIT(22))
#define EMAC_GMACJABBER_S 22
#define EMAC_GMACFRAMEBURST (BIT(21))
#define EMAC_GMACFRAMEBURST_S 21
#define EMAC_GMACJUMBOFRAME (BIT(20))
#define EMAC_GMACJUMBOFRAME_S 20
#define EMAC_GMACINTERFRAMEGAP 0x00000007
#define EMAC_GMACINTERFRAMEGAP_S 17
#define EMAC_GMACDISABLECRS (BIT(16))
#define EMAC_GMACDISABLECRS_S 16
#define EMAC_GMACMIIGMII (BIT(15))
#define EMAC_GMACMIIGMII_S 15
#define EMAC_GMACFESPEED (BIT(14))
#define EMAC_GMACFESPEED_S 14
#define EMAC_GMACRXOWN (BIT(13))
#define EMAC_GMACRXOWN_S 13
#define EMAC_GMACLOOPBACK (BIT(12))
#define EMAC_GMACLOOPBACK_S 12
#define EMAC_GMACDUPLEX (BIT(11))
#define EMAC_GMACDUPLEX_S 11
#define EMAC_GMACRXIPCOFFLOAD (BIT(10))
#define EMAC_GMACRXIPCOFFLOAD_S 10
#define EMAC_GMACRETRY (BIT(9))
#define EMAC_GMACRETRY_S 9
#define EMAC_GMACLINK (BIT(8))
#define EMAC_GMACLINK_S 8
#define EMAC_GMACPADCRCSTRIP (BIT(7))
#define EMAC_GMACPADCRCSTRIP_S 7
#define EMAC_GMACBACKOFFLIMIT 0x00000003
#define EMAC_GMACBACKOFFLIMIT_S 5
#define EMAC_GMACDEFERRALCHECK (BIT(4))
#define EMAC_GMACDEFERRALCHECK_S 4
#define EMAC_GMACTX (BIT(3))
#define EMAC_GMACTX_S 3
#define EMAC_GMACRX (BIT(2))
#define EMAC_GMACRX_S 2
#define EMAC_PREAMBLE_LENGTH_TRANSMIT_FRAMES 0x00000003
#define EMAC_PREAMBLE_LENGTH_TRANSMIT_FRAMES_S 0
#define EMAC_GMACFRAMEFILTER_REG (REG_EMAC_BASE + 0x1004)
#define EMAC_RECEIVEALL (BIT(31))
#define EMAC_RECEIVEALL_S 31
#define EMAC_DROP_NON_TCP_UDP_IP_FRAMES (BIT(21))
#define EMAC_DROP_NON_TCP_UDP_IP_FRAMES_S 21
#define EMAC_LAYER_3_AND_LAYER_4_FILTER_ENABLE (BIT(20))
#define EMAC_LAYER_3_AND_LAYER_4_FILTER_ENABLE_S 20
#define EMAC_VLAN_TAG_FILTER_ENABLE (BIT(16))
#define EMAC_VLAN_TAG_FILTER_ENABLE_S 16
#define EMAC_HASH_OR_PERFECT_FILTE (BIT(10))
#define EMAC_HASH_OR_PERFECT_FILTE_S 10
#define EMAC_SOURCE_ADDRESS_FILTER_ENABLE (BIT(9))
#define EMAC_SOURCE_ADDRESS_FILTER_ENABLE_S 9
#define EMAC_SA_INVERSE_FILTERING (BIT(8))
#define EMAC_SA_INVERSE_FILTERING_S 8
#define EMAC_PASS_CONTROL_FRAMES 0x00000003
#define EMAC_PASS_CONTROL_FRAMES_S 6
#define EMAC_DISABLE_BROADCAST_FRAMES (BIT(5))
#define EMAC_DISABLE_BROADCAST_FRAMES_S 5
#define EMAC_PASS_ALL_MULTICAST (BIT(4))
#define EMAC_PASS_ALL_MULTICAST_S 4
#define EMAC_DA_INVERSE_FILTERING (BIT(3))
#define EMAC_DA_INVERSE_FILTERING_S 3
#define EMAC_HASH_MULTICAST (BIT(2))
#define EMAC_HASH_MULTICAST_S 2
#define EMAC_HASH_UNICAST (BIT(1))
#define EMAC_HASH_UNICAST_S 1
#define EMAC_PROMISCUOUS_MODE (BIT(0))
#define EMAC_PROMISCUOUS_MODE_S 0
#define EMAC_GMACHASHHIGH_REG (REG_EMAC_BASE + 0x1008)
#define EMAC_HASH_TABLE_HIGH 0xFFFFFFFF
#define EMAC_HASH_TABLE_HIGH_S 0
#define EMAC_GMACHASHLOW_REG (REG_EMAC_BASE + 0x100C)
#define EMAC_HASH_TABLE_LOW 0xFFFFFFFF
#define EMAC_HASH_TABLE_LOW_S 0
#define EMAC_GMACGMIIADDR_REG (REG_EMAC_BASE + 0x1010)
#define EMAC_GMIIDEV 0x0000001F
#define EMAC_GMIIDEV_S 11
#define EMAC_GMIIREG 0x0000001F
#define EMAC_GMIIREG_S 6
#define EMAC_GMIICSRCLK 0x0000000F
#define EMAC_GMIICSRCLK_S 2
#define EMAC_GMIIWRITE (BIT(1))
#define EMAC_GMIIWRITE_S 1
#define EMAC_GMIIBUSY (BIT(0))
#define EMAC_GMIIBUSY_S 0
#define EMAC_GMACGMIIDATA_REG (REG_EMAC_BASE + 0x1014)
#define EMAC_GMII_DATA 0x0000FFFF
#define EMAC_GMII_DATA_S 0
#define EMAC_GMACFLOWCONTROL_REG (REG_EMAC_BASE + 0x1018)
#define EMAC_PAUSE_TIME 0x0000FFFF
#define EMAC_PAUSE_TIME_S 16
#define EMAC_DISABLE_ZERO_QUANTA_PAUSE (BIT(7))
#define EMAC_DISABLE_ZERO_QUANTA_PAUSE_S 7
#define EMAC_PAUSE_LOW_THRESHOLD 0x00000003
#define EMAC_PAUSE_LOW_THRESHOLD_S 4
#define EMAC_UNICAST_PAUSE_FRAME_DETECT (BIT(3))
#define EMAC_UNICAST_PAUSE_FRAME_DETECT_S 3
#define EMAC_RECEIVE_FLOW_CONTROL_ENABLE (BIT(2))
#define EMAC_RECEIVE_FLOW_CONTROL_ENABLE_S 2
#define EMAC_TRANSMIT_FLOW_CONTROL_ENABLE (BIT(1))
#define EMAC_TRANSMIT_FLOW_CONTROL_ENABLE_S 1
#define EMAC_FLOW_CONTROL_BUSY_BACKPRESSURE_ACTIVATE (BIT(0))
#define EMAC_FLOW_CONTROL_BUSY_BACKPRESSURE_ACTIVATE_S 0
#define EMAC_GMACVLAN_REG (REG_EMAC_BASE + 0x101C)
#define EMAC_VLAN_TAG_HASH_TABLE_MATCH_ENABLE (BIT(19))
#define EMAC_VLAN_TAG_HASH_TABLE_MATCH_ENABLE_S 19
#define EMAC_ENABLE_S_VLAN (BIT(18))
#define EMAC_ENABLE_S_VLAN_S 18
#define EMAC_VLAN_TAG_INVERSE_MATCH_ENABLE (BIT(17))
#define EMAC_VLAN_TAG_INVERSE_MATCH_ENABLE_S 17
#define EMAC_ENABLE_VLAN_TAG_COMPARISON (BIT(16))
#define EMAC_ENABLE_VLAN_TAG_COMPARISON_S 16
#define EMAC_VLAN_TAG_IDENTIFIER_RECEIVE_FRAMES 0x0000FFFF
#define EMAC_VLAN_TAG_IDENTIFIER_RECEIVE_FRAMES_S 0
#define EMAC_GMACVERSION_REG (REG_EMAC_BASE + 0x1020)
#define EMAC_USERVER 0x000000FF
#define EMAC_USERVER_S 8
#define EMAC_SNPSVER 0x000000FF
#define EMAC_SNPSVER_S 0
#define EMAC_GMACDEBUG_REG (REG_EMAC_BASE + 0x1024)
#define EMAC_MTL_TXSTATUS_FIFO_FULL_STATUS (BIT(25))
#define EMAC_MTL_TXSTATUS_FIFO_FULL_STATUS_S 25
#define EMAC_MTL_TX_FIFO_NOT_EMPTY_STATUS (BIT(24))
#define EMAC_MTL_TX_FIFO_NOT_EMPTY_STATUS_S 24
#define EMAC_MTL_TX_FIFO_WRITE_CONTROLLER_STATUS (BIT(22))
#define EMAC_MTL_TX_FIFO_WRITE_CONTROLLER_STATUS_S 22
#define EMAC_MTL_TX_FIFO_READ_CONTROLLER_STATUS 0x00000003
#define EMAC_MTL_TX_FIFO_READ_CONTROLLER_STATUS_S 20
#define EMAC_MAC_TRANSMITTER_PAUSE (BIT(19))
#define EMAC_MAC_TRANSMITTER_PAUSE_S 19
#define EMAC_MAC_TRANSMIT_FRAME_CONTROLLER_STATUS 0x00000003
#define EMAC_MAC_TRANSMIT_FRAME_CONTROLLER_STATUS_S 17
#define EMAC_MAC_TRANSMIT_PROTOCOL_ENGINE_STATUS (BIT(16))
#define EMAC_MAC_TRANSMIT_PROTOCOL_ENGINE_STATUS_S 16
#define EMAC_MTL_RXFIFO_FILL_LEVEL_STATUS 0x00000003
#define EMAC_MTL_RXFIFO_FILL_LEVEL_STATUS_S 8
#define EMAC_MTL_RXFIFO_READ_CONTROLLER_STATE 0x00000003
#define EMAC_MTL_RXFIFO_READ_CONTROLLER_STATE_S 5
#define EMAC_MTL_RX_FIFO_WRITE_CONTROLLER_ACTIVE_STATUS (BIT(4))
#define EMAC_MTL_RX_FIFO_WRITE_CONTROLLER_ACTIVE_STATUS_S 4
#define EMAC_MAC_RECEIVE_FRAME_FIFO_CONTROLLER_STATUS 0x00000003
#define EMAC_MAC_RECEIVE_FRAME_FIFO_CONTROLLER_STATUS_S 1
#define EMAC_MAC_RECEIVE_PROTOCOL_ENGINE_STATUS (BIT(0))
#define EMAC_MAC_RECEIVE_PROTOCOL_ENGINE_STATUS_S 0
#define EMAC_GMACLPITIMERSCONTROL_REG (REG_EMAC_BASE + 0x1034)
#define EMAC_LPI_LS_TIMER 0x000003FF
#define EMAC_LPI_LS_TIMER_S 16
#define EMAC_LPI_TW_TIMER 0x0000FFFF
#define EMAC_LPI_TW_TIMER_S 0
#define EMAC_GMACINTERRUPTSTATUS_REG (REG_EMAC_BASE + 0x1038)
#define EMAC_GPI_INTERRUPT_STATUS (BIT(11))
#define EMAC_GPI_INTERRUPT_STATUS_S 11
#define EMAC_LPI_INTERRUPT_STATUS (BIT(10))
#define EMAC_LPI_INTERRUPT_STATUS_S 10
#define EMAC_TIMESTAMP_INTERRUP_STATUS (BIT(9))
#define EMAC_TIMESTAMP_INTERRUP_STATUS_S 9
#define EMAC_MMC_RECEIVE_CHECKSUM_OFFLOAD_INTERRUPT_STATUS (BIT(7))
#define EMAC_MMC_RECEIVE_CHECKSUM_OFFLOAD_INTERRUPT_STATUS_S 7
#define EMAC_MMC_TRANSMIT_INTERRUPT_STATUS (BIT(6))
#define EMAC_MMC_TRANSMIT_INTERRUPT_STATUS_S 6
#define EMAC_MMC_RECEIVE_INTERRUPT_STATUS (BIT(5))
#define EMAC_MMC_RECEIVE_INTERRUPT_STATUS_S 5
#define EMAC_MMC_INTERRUPT_STATUS (BIT(4))
#define EMAC_MMC_INTERRUPT_STATUS_S 4
#define EMAC_PMT_INTERRUPT_STATUS (BIT(3))
#define EMAC_PMT_INTERRUPT_STATUS_S 3
#define EMAC_PCS_AUTO_NEGOTIATION_COMPLETE (BIT(2))
#define EMAC_PCS_AUTO_NEGOTIATION_COMPLETE_S 2
#define EMAC_PCS_LINK_STATUS_CHANGED (BIT(1))
#define EMAC_PCS_LINK_STATUS_CHANGED_S 1
#define EMAC_INTERRUPT_STATUS (BIT(0))
#define EMAC_INTERRUPT_STATUS_S 0
#define EMAC_GMACINTERRUPTMASK_REG (REG_EMAC_BASE + 0x103C)
#define EMAC_LPI_INTERRUPT_MASK (BIT(10))
#define EMAC_LPI_INTERRUPT_MASK_S 10
#define EMAC_TIMESTAMP_INTERRUPT_MASK (BIT(9))
#define EMAC_TIMESTAMP_INTERRUPT_MASK_S 9
#define EMAC_PMT_INTERRUPT_MASK (BIT(3))
#define EMAC_PMT_INTERRUPT_MASK_S 3
#define EMAC_PCS_AN_COMPLETION_INTERRUPT_MASK (BIT(2))
#define EMAC_PCS_AN_COMPLETION_INTERRUPT_MASK_S 2
#define EMAC_PCS_LINK_STATUS_INTERRUPT_MASK (BIT(1))
#define EMAC_PCS_LINK_STATUS_INTERRUPT_MASK_S 1
#define EMAC_INTERRUPT_MASK (BIT(0))
#define EMAC_INTERRUPT_MASK_S 0
#define EMAC_GMACADDR0HIGH_REG (REG_EMAC_BASE + 0x1040)
#define EMAC_ADDRESS_ENABLE0 (BIT(31))
#define EMAC_ADDRESS_ENABLE0_S 31
#define EMAC_MAC_ADDRESS0_HI 0x0000FFFF
#define EMAC_MAC_ADDRESS0_HI_S 0
#define EMAC_GMACADDR0LOW_REG (REG_EMAC_BASE + 0x1044)
#define EMAC_MAC_ADDRESS0_LOW 0xFFFFFFFF
#define EMAC_MAC_ADDRESS0_LOW_S 0
#define EMAC_GMACADDR1HIGH_REG (REG_EMAC_BASE + 0x1048)
#define EMAC_ADDRESS_ENABLE1 (BIT(31))
#define EMAC_ADDRESS_ENABLE1_S 31
#define EMAC_SOURCE_ADDRESS (BIT(30))
#define EMAC_SOURCE_ADDRESS_S 30
#define EMAC_MASK_BYTE_CONTROL 0x0000003F
#define EMAC_MASK_BYTE_CONTROL_S 24
#define EMAC_MAC_ADDRESS1_HI 0x0000FFFF
#define EMAC_MAC_ADDRESS1_HI_S 0
#define EMAC_GMACADDR1LOW_REG (REG_EMAC_BASE + 0x104C)
#define EMAC_MAC_ADDRESS1_LOW 0xFFFFFFFF
#define EMAC_MAC_ADDRESS1_LOW_S 0
#define EMAC_GMAC_AN_CONTROL_REG (REG_EMAC_BASE + 0x10C0)
#define EMAC_SGMII_RAL_CONTROL (BIT(18))
#define EMAC_SGMII_RAL_CONTROL_S 18
#define EMAC_LOCK_REFERENCE (BIT(17))
#define EMAC_LOCK_REFERENCE_S 17
#define EMAC_ENABLE_COMMA_DETECT (BIT(16))
#define EMAC_ENABLE_COMMA_DETECT_S 16
#define EMAC_EXTERNAL_LOOPBACK_ENABLE (BIT(14))
#define EMAC_EXTERNAL_LOOPBACK_ENABLE_S 14
#define EMAC_AUTO_NEGOTIATION_ENABLE (BIT(12))
#define EMAC_AUTO_NEGOTIATION_ENABLE_S 12
#define EMAC_RESTART_AUTO_NEGOTIATION (BIT(9))
#define EMAC_RESTART_AUTO_NEGOTIATION_S 9
#define EMAC_GMAC_AN_STATUS_REG (REG_EMAC_BASE + 0x10C4)
#define EMAC_EXTENDED_STATUS (BIT(8))
#define EMAC_EXTENDED_STATUS_S 8
#define EMAC_AUTO_NEGOTIATION_COMPLETE (BIT(5))
#define EMAC_AUTO_NEGOTIATION_COMPLETE_S 5
#define EMAC_AUTO_NEGOTIATION_ABILITY (BIT(3))
#define EMAC_AUTO_NEGOTIATION_ABILITY_S 3
#define EMAC_LINK_AN_STATUS (BIT(2))
#define EMAC_LINK_AN_STATUS_S 2
#define EMAC_GMAC_AUTO_NEGOTIATION_ADVERTISEMENT_REG (REG_EMAC_BASE + 0x10C8)
#define EMAC_ADV_NEXT_PAGE_SUPPORT (BIT(15))
#define EMAC_ADV_NEXT_PAGE_SUPPORT_S 15
#define EMAC_ADV_REMOTE_FAULT_ENCODING 0x00000003
#define EMAC_ADV_REMOTE_FAULT_ENCODING_S 12
#define EMAC_ADV_PAUSE_ENCODING 0x00000003
#define EMAC_ADV_PAUSE_ENCODING_S 7
#define EMAC_ADV_HALF_DUPLEX (BIT(6))
#define EMAC_ADV_HALF_DUPLEX_S 6
#define EMAC_ADV_FULL_DUPLEX (BIT(5))
#define EMAC_ADV_FULL_DUPLEX_S 5
#define EMAC_GMAC_AUTO_NEGOTIATION_LINK_PARTNER_ABILITY_REG (REG_EMAC_BASE + 0x10CC)
#define EMAC_LINK_NEXT_PAGE_SUPPORT (BIT(15))
#define EMAC_LINK_NEXT_PAGE_SUPPORT_S 15
#define EMAC_LINK_ACKNOWLEDGE (BIT(14))
#define EMAC_LINK_ACKNOWLEDGE_S 14
#define EMAC_LINK_REMOTE_FAULT_ENCODING 0x00000003
#define EMAC_LINK_REMOTE_FAULT_ENCODING_S 12
#define EMAC_LINK_PAUSE_ENCODING 0x00000003
#define EMAC_LINK_PAUSE_ENCODING_S 7
#define EMAC_LINK_HALF_DUPLEX (BIT(6))
#define EMAC_LINK_HALF_DUPLEX_S 6
#define EMAC_LINK_FULL_DUPLEX (BIT(5))
#define EMAC_LINK_FULL_DUPLEX_S 5
#define EMAC_GMAC_AUTO_NEGOTIATION_EXPANSION_REG (REG_EMAC_BASE + 0x10D0)
#define EMAC_NEXT_PAGE_ABILITY (BIT(2))
#define EMAC_NEXT_PAGE_ABILITY_S 2
#define EMAC_NEW_PAGE_RECEIVED (BIT(1))
#define EMAC_NEW_PAGE_RECEIVED_S 1
#define EMAC_GMAC_TBI_EXTENDED_STATUS_REG (REG_EMAC_BASE + 0x10D4)
#define EMAC_1000BASE_X_FULL_DUPLEX_CAPABLE (BIT(15))
#define EMAC_1000BASE_X_FULL_DUPLEX_CAPABLE_S 15
#define EMAC_1000BASE_X_HALF_DUPLEX_CAPABLE (BIT(14))
#define EMAC_1000BASE_X_HALF_DUPLEX_CAPABLE_S 14
#define EMAC_GMAC_CONTROL_STATUS_REG (REG_EMAC_BASE + 0x10D8)
#define EMAC_SMIDRXS (BIT(16))
#define EMAC_SMIDRXS_S 16
#define EMAC_FALSE_CARRIER_DETECTED (BIT(5))
#define EMAC_FALSE_CARRIER_DETECTED_S 5
#define EMAC_JABBER_TIMEOUT (BIT(4))
#define EMAC_JABBER_TIMEOUT_S 4
#define EMAC_LINK_STATUS (BIT(3))
#define EMAC_LINK_STATUS_S 3
#define EMAC_LINK_SPEED 0x00000003
#define EMAC_LINK_SPEED_S 1
#define EMAC_LINK_MODE (BIT(0))
#define EMAC_LINK_MODE_S 0
#define EMAC_GMAC_WATCHDOG_TIMEOUT_REG (REG_EMAC_BASE + 0x10DC)
#define EMAC_PROGRAMMABLE_WATCHDOG_ENABLE (BIT(16))
#define EMAC_PROGRAMMABLE_WATCHDOG_ENABLE_S 16
#define EMAC_WATCHDOG_TIMEOUT 0x00003FFF
#define EMAC_WATCHDOG_TIMEOUT_S 0
#define EMAC_GMAC_GENERAL_PURPOSE_IO_REG (REG_EMAC_BASE + 0x10E0)
#define EMAC_GPI_TYPE 0x0000000F
#define EMAC_GPI_TYPE_S 24
#define EMAC_GPI_INTERRUPT_ENABLE 0x0000000F
#define EMAC_GPI_INTERRUPT_ENABLE_S 16
#define EMAC_GENERAL_PURPOSE_OUTPUT 0x0000000F
#define EMAC_GENERAL_PURPOSE_OUTPUT_S 8
#define EMAC_GENERAL_PURPOSE_INPUT_STATUS 0x0000000F
#define EMAC_GENERAL_PURPOSE_INPUT_STATUS_S 0
#define EMAC_GMAC_LAYER3_LAYER4_CONTROL0_REG (REG_EMAC_BASE + 0x1400)
#define EMAC_LAYER4_DESTINATION_PORT_INVERSE_MATCH_ENABLE (BIT(21))
#define EMAC_LAYER4_DESTINATION_PORT_INVERSE_MATCH_ENABLE_S 21
#define EMAC_LAYER4_DESTINATION_PORT_MATCH_ENABLE (BIT(20))
#define EMAC_LAYER4_DESTINATION_PORT_MATCH_ENABLE_S 20
#define EMAC_LAYER4_SOURCE_PORT_INVERSE_MATCH_ENABLE (BIT(19))
#define EMAC_LAYER4_SOURCE_PORT_INVERSE_MATCH_ENABLE_S 19
#define EMAC_LAYER4_SOURCE_PORT_MATCH_ENABLE (BIT(18))
#define EMAC_LAYER4_SOURCE_PORT_MATCH_ENABLE_S 18
#define EMAC_LAYER4_PROTOCOL_ENABLE (BIT(16))
#define EMAC_LAYER4_PROTOCOL_ENABLE_S 16
#define EMAC_LAYER3_IP_DA_HIGHER_BITS_MATCH 0x0000001F
#define EMAC_LAYER3_IP_DA_HIGHER_BITS_MATCH_S 11
#define EMAC_LAYER3_IP_SA_HIGHER_BITS_MATCH 0x0000001F
#define EMAC_LAYER3_IP_SA_HIGHER_BITS_MATCH_S 6
#define EMAC_LAYER3_IP_DA_INVERSE_MATCH_ENABLE (BIT(5))
#define EMAC_LAYER3_IP_DA_INVERSE_MATCH_ENABLE_S 5
#define EMAC_LAYER3_IP_DA_MATCH_ENABLE (BIT(4))
#define EMAC_LAYER3_IP_DA_MATCH_ENABLE_S 4
#define EMAC_LAYER3_IP_SA_INVERSE_MATCH_ENABLE (BIT(3))
#define EMAC_LAYER3_IP_SA_INVERSE_MATCH_ENABLE_S 3
#define EMAC_LAYER3_IP_SA_MATCH_ENABLE (BIT(2))
#define EMAC_LAYER3_IP_SA_MATCH_ENABLE_S 2
#define EMAC_LAYER3_PROTOCOL_ENABLE (BIT(0))
#define EMAC_LAYER3_PROTOCOL_ENABLE_S 0
#define EMAC_GMAC_LAYER4_ADDRESS0_REG (REG_EMAC_BASE + 0x1404)
#define EMAC_LAYER4_DESTINATION_PORT_NUMBER_FIELD 0x0000FFFF
#define EMAC_LAYER4_DESTINATION_PORT_NUMBER_FIELD_S 16
#define EMAC_LAYER4_SOURCE_PORT_NUMBER_FIELD 0x0000FFFF
#define EMAC_LAYER4_SOURCE_PORT_NUMBER_FIELD_S 0
#define EMAC_GMAC_LAYER3_ADDRESS0_REG (REG_EMAC_BASE + 0x1410)
#define EMAC_LAYER3_ADDRESS0_FIELD 0xFFFFFFFF
#define EMAC_LAYER3_ADDRESS0_FIELD_S 0
#define EMAC_GMAC_LAYER3_ADDRESS1_REG (REG_EMAC_BASE + 0x1414)
#define EMAC_LAYER3_ADDRESS1_FIELD 0xFFFFFFFF
#define EMAC_LAYER3_ADDRESS1_FIELD_S 0
#define EMAC_GMAC_LAYER3_ADDRESS2_REG (REG_EMAC_BASE + 0x1418)
#define EMAC_LAYER3_ADDRESS2_FIELD 0xFFFFFFFF
#define EMAC_LAYER3_ADDRESS2_FIELD_S 0
#define EMAC_GMAC_LAYER3_ADDRESS3_REG (REG_EMAC_BASE + 0x141C)
#define EMAC_LAYER3_ADDRESS3_FIELD 0xFFFFFFFF
#define EMAC_LAYER3_ADDRESS3_FIELD_S 0
#define EMAC_GMAC_HASH_TABLE0_REG (REG_EMAC_BASE + 0x1500)
#define EMAC_FIRST32_BITS_HASH_TABLE 0xFFFFFFFF
#define EMAC_FIRST32_BITS_HASH_TABLE_S 0
#define EMAC_GMAC_VLAN_TAG_INCLUSION_REPLACEMENT_REG (REG_EMAC_BASE + 0x1584)
#define EMAC_VLAN_C_VLAN_S_VLAN (BIT(19))
#define EMAC_VLAN_C_VLAN_S_VLAN_S 19
#define EMAC_VLAN_PRIORITY_CONTROL (BIT(18))
#define EMAC_VLAN_PRIORITY_CONTROL_S 18
#define EMAC_VLAN_TAG_CONTROL_TRANSMIT_FRAMES 0x00000003
#define EMAC_VLAN_TAG_CONTROL_TRANSMIT_FRAMES_S 16
#define EMAC_VLAN_TAG_TRANSMIT_FRAMES 0x0000FFFF
#define EMAC_VLAN_TAG_TRANSMIT_FRAMES_S 0
#define EMAC_GMAC_VLAN_HASH_TABLE_REG (REG_EMAC_BASE + 0x1588)
#define EMAC_VLAN_HASH_TABLE 0x0000FFFF
#define EMAC_VLAN_HASH_TABLE_S 0
#ifdef __cplusplus
}
#endif
#endif

27
tools/sdk/include/esp32/soc/hwcrypto_reg.h
View File

@ -30,8 +30,31 @@
#define RSA_MULT_MODE_REG (DR_REG_RSA_BASE + 0x80c)
#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x810)
#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0X814)
#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x814)
#define RSA_CLEAN_ADDR (DR_REG_RSA_BASE + 0X818)
#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x818)
/* SHA acceleration registers */
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x00)
#define SHA_1_START_REG ((DR_REG_SHA_BASE) + 0x80)
#define SHA_1_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x84)
#define SHA_1_LOAD_REG ((DR_REG_SHA_BASE) + 0x88)
#define SHA_1_BUSY_REG ((DR_REG_SHA_BASE) + 0x8c)
#define SHA_256_START_REG ((DR_REG_SHA_BASE) + 0x90)
#define SHA_256_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x94)
#define SHA_256_LOAD_REG ((DR_REG_SHA_BASE) + 0x98)
#define SHA_256_BUSY_REG ((DR_REG_SHA_BASE) + 0x9c)
#define SHA_384_START_REG ((DR_REG_SHA_BASE) + 0xa0)
#define SHA_384_CONTINUE_REG ((DR_REG_SHA_BASE) + 0xa4)
#define SHA_384_LOAD_REG ((DR_REG_SHA_BASE) + 0xa8)
#define SHA_384_BUSY_REG ((DR_REG_SHA_BASE) + 0xac)
#define SHA_512_START_REG ((DR_REG_SHA_BASE) + 0xb0)
#define SHA_512_CONTINUE_REG ((DR_REG_SHA_BASE) + 0xb4)
#define SHA_512_LOAD_REG ((DR_REG_SHA_BASE) + 0xb8)
#define SHA_512_BUSY_REG ((DR_REG_SHA_BASE) + 0xbc)
#endif

4
tools/sdk/include/esp32/soc/soc.h
View File

@ -142,6 +142,7 @@
#define DR_REG_DPORT_BASE 0x3ff00000
#define DR_REG_RSA_BASE 0x3ff02000
#define DR_REG_SHA_BASE 0x3ff03000
#define DR_REG_UART_BASE 0x3ff40000
#define DR_REG_SPI1_BASE 0x3ff42000
#define DR_REG_SPI0_BASE 0x3ff43000
@ -270,7 +271,7 @@
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software Reserved Reserved
* 8 1 extern level BLE Controller
* 9 1 extern level
* 9 1 extern level EMAC
* 10 1 extern edge Internal Timer
* 11 3 profiling
* 12 1 extern level
@ -302,6 +303,7 @@
#define ETS_FROM_CPU_INUM 2
#define ETS_T0_WDT_INUM 3
#define ETS_WBB_INUM 4
#define ETS_EMAC_INUM 9
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24

167
tools/sdk/include/ethernet/esp_eth.h Normal file
View File

@ -0,0 +1,167 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_ETH_H__
#define __ESP_ETH_H__
#include <stdint.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*eth_phy_fun)(void);
typedef esp_err_t (*eth_tcpip_input_fun)(void *buffer, uint16_t len, void *eb);
typedef void (*eth_gpio_config_func)(void);
typedef enum {
ETH_MODE_RMII = 0,
ETH_MDOE_MII,
} eth_mode_t;
typedef enum {
PHY0 = 0,
PHY1,
PHY2,
PHY3,
PHY4,
PHY5,
PHY6,
PHY7,
PHY8,
PHY9,
PHY10,
PHY11,
PHY12,
PHY13,
PHY14,
PHY15,
PHY16,
PHY17,
PHY18,
PHY19,
PHY20,
PHY21,
PHY22,
PHY23,
PHY24,
PHY25,
PHY26,
PHY27,
PHY28,
PHY29,
PHY30,
PHY31,
} eth_phy_base_t;
/**
* @brief ethernet configuration
*
*/
typedef struct {
eth_phy_base_t phy_addr; /*!< phy base addr (0~31) */
eth_mode_t mac_mode; /*!< mac mode only support RMII now */
eth_tcpip_input_fun tcpip_input; /*!< tcpip input func */
eth_phy_fun phy_init; /*!< phy init func */
eth_gpio_config_func gpio_config; /*!< gpio config func */
} eth_config_t;
/**
* @brief Init ethernet mac
*
* @note config can not be NULL,and phy chip must be suitable to phy init func.
*
* @param[in] config mac init data.
*
* @return
* - ESP_OK
* - ESP_FAIL
*/
esp_err_t esp_eth_init(eth_config_t *config);
/**
* @brief Send packet from tcp/ip to mac
*
* @note buf can not be NULL,size must be less than 1580
*
* @param[in] buf: start address of packet data.
*
* @param[in] size: size (byte) of packet data.
*
* @return
* - ESP_OK
* - ESP_FAIL
*/
esp_err_t esp_eth_tx(uint8_t *buf, uint16_t size);
/**
* @brief Enable ethernet interface
*
* @note Shout be called after esp_eth_init
*
* @return
* - ESP_OK
* - ESP_FAIL
*/
esp_err_t esp_eth_enable(void);
/**
* @brief Disable ethernet interface
*
* @note Shout be called after esp_eth_init
*
* @return
* - ESP_OK
* - ESP_FAIL
*/
esp_err_t esp_eth_disable(void);
/**
* @brief Get mac addr
*
* @note mac addr must be a valid unicast address
*
* @param[out] mac: start address of mac address.
*/
void esp_eth_get_mac(uint8_t mac[6]);
/**
* @brief Read phy reg with smi interface.
*
* @note phy base addr must be right.
*
* @param[in] reg_num: phy reg num.
*
* @param[in] value: value which write to phy reg.
*/
void esp_eth_smi_write(uint32_t reg_num, uint16_t value);
/**
* @brief Write phy reg with smi interface.
*
* @note phy base addr must be right.
*
* @param[in] reg_num: phy reg num.
*
* @return value what read from phy reg
*/
uint16_t esp_eth_smi_read(uint32_t reg_num);
#ifdef __cplusplus
}
#endif
#endif

8
tools/sdk/include/lwip/lwip/dhcp.h
View File

@ -96,7 +96,11 @@ struct dhcp
#endif /* LWIP_DHCP_BOOTPFILE */
/* Espressif add start. */
#ifdef ESP_LWIP
void (*cb)(struct netif*); /* callback for dhcp, add a parameter to show dhcp status if needed */
#else
void (*cb)(void); /* callback for dhcp, add a parameter to show dhcp status if needed */
#endif
/* Espressif add end. */
};
@ -146,7 +150,11 @@ void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp);
void dhcp_cleanup(struct netif *netif);
/* Espressif add start. */
/** set callback for DHCP */
#ifdef ESP_LWIP
void dhcp_set_cb(struct netif *netif, void (*cb)(struct netif*));
#else
void dhcp_set_cb(struct netif *netif, void (*cb)(void));
#endif
/* Espressif add end. */
/** start DHCP configuration */
err_t dhcp_start(struct netif *netif);

1
tools/sdk/include/lwip/lwip/lwip_debug.h
View File

@ -20,5 +20,6 @@ void dbg_lwip_tcp_pcb_show(void);
void dbg_lwip_udp_pcb_show(void);
void dbg_lwip_tcp_rxtx_show(void);
void dbg_lwip_udp_rxtx_show(void);
void dbg_lwip_mem_cnt_show(void);
#endif

17
tools/sdk/include/lwip/lwip/memp.h
View File

@ -71,8 +71,25 @@ extern const struct memp_desc* const memp_pools[MEMP_MAX];
#include "lwip/mem.h"
#define memp_init()
#if ESP_CNT_DEBUG
static inline void* memp_malloc(int type)
{
ESP_CNT_MEM_MALLOC_INC(type);
return mem_malloc(memp_pools[type]->size);
}
static inline void memp_free(int type, void *mem)
{
ESP_CNT_MEM_FREE_INC(type);
mem_free(mem);
}
//#define memp_malloc(type) mem_malloc(memp_pools[type]->size); ESP_CNT_MEM_MALLOC_INC(type)
//#define memp_free(type, mem) mem_free(mem); ESP_CNT_MEM_FREE_INC(type)
#else
#define memp_malloc(type) mem_malloc(memp_pools[type]->size)
#define memp_free(type, mem) mem_free(mem)
#endif
#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \
const struct memp_desc memp_ ## name = { \

10
tools/sdk/include/lwip/lwip/priv/memp_priv.h
View File

@ -140,6 +140,16 @@ struct memp_desc {
#endif /* MEMP_MEM_MALLOC */
};
#if (ESP_CNT_DEBUG == 1)
extern uint32_t g_lwip_mem_cnt[MEMP_MAX][2];
#define ESP_CNT_MEM_MALLOC_INC(type) g_lwip_mem_cnt[type][0]++
#define ESP_CNT_MEM_FREE_INC(type) g_lwip_mem_cnt[type][1]++
#else
#define ESP_CNT_MEM_MALLOC_INC(type)
#define ESP_CNT_MEM_FREE_INC(type)
#endif
#ifdef LWIP_DEBUG
#define DECLARE_LWIP_MEMPOOL_DESC(desc) (desc),
#else

30
tools/sdk/include/lwip/lwip/stats.h
View File

@ -213,6 +213,23 @@ struct stats_mib2_netif_ctrs {
u32_t ifouterrors;
};
struct stats_esp {
/* mbox post fail stats */
u32_t rx_rawmbox_post_fail;
u32_t rx_udpmbox_post_fail;
u32_t rx_tcpmbox_post_fail;
u32_t err_tcp_rxmbox_post_fail;
u32_t err_tcp_acceptmbox_post_fail;
u32_t acceptmbox_post_fail;
u32_t free_mbox_post_fail;
u32_t tcpip_inpkt_post_fail;
u32_t tcpip_cb_post_fail;
/* memory malloc/free/failed stats */
u32_t wlanif_input_pbuf_fail;
u32_t wlanif_outut_pbuf_fail;
};
struct stats_ {
#if LINK_STATS
struct stats_proto link;
@ -265,6 +282,9 @@ struct stats_ {
#if MIB2_STATS
struct stats_mib2 mib2;
#endif
#if ESP_STATS
struct stats_esp esp;
#endif
};
extern struct stats_ lwip_stats;
@ -438,6 +458,14 @@ void stats_init(void);
#define MIB2_STATS_INC(x)
#endif
#if ESP_STATS
#define ESP_STATS_INC(x) STATS_INC(x)
#define ESP_STATS_DISPLAY() stats_display_esp(&lwip_stats.esp);
#else
#define ESP_STATS_INC(x)
#define ESP_STATS_DISPLAY()
#endif
/* Display of statistics */
#if LWIP_STATS_DISPLAY
void stats_display(void);
@ -446,6 +474,7 @@ void stats_display_igmp(struct stats_igmp *igmp, const char *name);
void stats_display_mem(struct stats_mem *mem, const char *name);
void stats_display_memp(struct stats_mem *mem, int index);
void stats_display_sys(struct stats_sys *sys);
void stats_display_esp(struct stats_esp *esp);
#else /* LWIP_STATS_DISPLAY */
#define stats_display()
#define stats_display_proto(proto, name)
@ -453,6 +482,7 @@ void stats_display_sys(struct stats_sys *sys);
#define stats_display_mem(mem, name)
#define stats_display_memp(mem, index)
#define stats_display_sys(sys)
#define stats_display_esp(esp)
#endif /* LWIP_STATS_DISPLAY */
#ifdef __cplusplus

11
tools/sdk/include/lwip/lwipopts.h
View File

@ -379,22 +379,21 @@
* The queue size value itself is platform-dependent, but is passed to
* sys_mbox_new() when tcpip_init is called.
*/
#define TCPIP_MBOX_SIZE 16
#define TCPIP_MBOX_SIZE 32
/**
* DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
* NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
* to sys_mbox_new() when the recvmbox is created.
*/
#define DEFAULT_UDP_RECVMBOX_SIZE 16
#define DEFAULT_UDP_RECVMBOX_SIZE 6
/**
* DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
* NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
* to sys_mbox_new() when the recvmbox is created.
*/
#define DEFAULT_TCP_RECVMBOX_SIZE 16
//#define DEFAULT_TCP_RECVMBOX_SIZE 6
#define DEFAULT_TCP_RECVMBOX_SIZE 6
/**
* DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
@ -556,6 +555,7 @@
*/
#define TCPIP_DEBUG LWIP_DBG_OFF
/* Enable all Espressif-only options */
#define ESP_LWIP 1
@ -571,6 +571,8 @@
#define ESP_IP4_ATON 1
#define ESP_LIGHT_SLEEP 1
#define ESP_L2_TO_L3_COPY CONFIG_L2_TO_L3_COPY
#define ESP_CNT_DEBUG 0
#define ESP_DUAL_CORE 0
#define TCP_WND_DEFAULT (4*TCP_MSS)
#define TCP_SND_BUF_DEFAULT (2*TCP_MSS)
@ -593,7 +595,6 @@ extern unsigned char misc_prof_get_tcp_snd_buf(void);
#define DHCP_DEBUG LWIP_DBG_OFF
#define LWIP_DEBUG LWIP_DBG_OFF
#define TCP_DEBUG LWIP_DBG_OFF
#define ESP_THREAD_SAFE_DEBUG LWIP_DBG_OFF
#define CHECKSUM_CHECK_UDP 0
#define CHECKSUM_CHECK_IP 0

35
tools/sdk/include/lwip/netif/ethernetif.h Executable file
View File

@ -0,0 +1,35 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ETH_LWIP_IF_H_
#define _ETH_LWIP_IF_H_
#include "lwip/err.h"
#ifdef __cplusplus
extern "C" {
#endif
err_t ethernetif_init(struct netif *netif);
void ethernetif_input(struct netif *netif, void *buffer, u16_t len);
void netif_reg_addr_change_cb(void* cb);
#ifdef __cplusplus
}
#endif
#endif /* _ETH_LWIP_IF_H_ */

18
tools/sdk/include/lwip/netif/wlanif.h
View File

@ -1,7 +1,17 @@
/*
* Copyright (c) 2010-2011 Espressif System
*
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _WLAN_LWIP_IF_H_
#define _WLAN_LWIP_IF_H_

11
tools/sdk/include/lwip/port/lwipopts.h
View File

@ -379,22 +379,21 @@
* The queue size value itself is platform-dependent, but is passed to
* sys_mbox_new() when tcpip_init is called.
*/
#define TCPIP_MBOX_SIZE 16
#define TCPIP_MBOX_SIZE 32
/**
* DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
* NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
* to sys_mbox_new() when the recvmbox is created.
*/
#define DEFAULT_UDP_RECVMBOX_SIZE 16
#define DEFAULT_UDP_RECVMBOX_SIZE 6
/**
* DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
* NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
* to sys_mbox_new() when the recvmbox is created.
*/
#define DEFAULT_TCP_RECVMBOX_SIZE 16
//#define DEFAULT_TCP_RECVMBOX_SIZE 6
#define DEFAULT_TCP_RECVMBOX_SIZE 6
/**
* DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
@ -556,6 +555,7 @@
*/
#define TCPIP_DEBUG LWIP_DBG_OFF
/* Enable all Espressif-only options */
#define ESP_LWIP 1
@ -571,6 +571,8 @@
#define ESP_IP4_ATON 1
#define ESP_LIGHT_SLEEP 1
#define ESP_L2_TO_L3_COPY CONFIG_L2_TO_L3_COPY
#define ESP_CNT_DEBUG 0
#define ESP_DUAL_CORE 0
#define TCP_WND_DEFAULT (4*TCP_MSS)
#define TCP_SND_BUF_DEFAULT (2*TCP_MSS)
@ -593,7 +595,6 @@ extern unsigned char misc_prof_get_tcp_snd_buf(void);
#define DHCP_DEBUG LWIP_DBG_OFF
#define LWIP_DEBUG LWIP_DBG_OFF
#define TCP_DEBUG LWIP_DBG_OFF
#define ESP_THREAD_SAFE_DEBUG LWIP_DBG_OFF
#define CHECKSUM_CHECK_UDP 0
#define CHECKSUM_CHECK_IP 0

35
tools/sdk/include/lwip/port/netif/ethernetif.h Executable file
View File

@ -0,0 +1,35 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ETH_LWIP_IF_H_
#define _ETH_LWIP_IF_H_
#include "lwip/err.h"
#ifdef __cplusplus
extern "C" {
#endif
err_t ethernetif_init(struct netif *netif);
void ethernetif_input(struct netif *netif, void *buffer, u16_t len);
void netif_reg_addr_change_cb(void* cb);
#ifdef __cplusplus
}
#endif
#endif /* _ETH_LWIP_IF_H_ */

18
tools/sdk/include/lwip/port/netif/wlanif.h
View File

@ -1,7 +1,17 @@
/*
* Copyright (c) 2010-2011 Espressif System
*
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _WLAN_LWIP_IF_H_
#define _WLAN_LWIP_IF_H_

13
tools/sdk/include/mbedtls/mbedtls/esp_config.h
View File

@ -243,11 +243,14 @@
#define MBEDTLS_AES_ALT
#endif
/* Currently hardware SHA does not work with TLS handshake,
due to concurrency issue. Internal TW#7111. */
//#define MBEDTLS_SHA1_ALT
//#define MBEDTLS_SHA256_ALT
//#define MBEDTLS_SHA512_ALT
/* MBEDTLS_SHAxx_ALT to enable hardware SHA support
with software fallback.
*/
#ifdef CONFIG_MBEDTLS_HARDWARE_SHA
#define MBEDTLS_SHA1_ALT
#define MBEDTLS_SHA256_ALT
#define MBEDTLS_SHA512_ALT
#endif
/* The following MPI (bignum) functions have ESP32 hardware support,
Uncommenting these macros will use the hardware-accelerated

109
tools/sdk/include/mbedtls/sha1_alt.h
View File

@ -1,16 +1,25 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SHA-1 implementation with hardware ESP32 support added.
* Uses mbedTLS software implementation for failover when concurrent
* SHA operations are in use.
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE LTD
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef _SHA1_ALT_H_
#define _SHA1_ALT_H_
@ -20,17 +29,73 @@ extern "C" {
#if defined(MBEDTLS_SHA1_ALT)
#include "hwcrypto/sha.h"
typedef enum {
ESP_MBEDTLS_SHA1_UNUSED, /* first block hasn't been processed yet */
ESP_MBEDTLS_SHA1_HARDWARE, /* using hardware SHA engine */
ESP_MBEDTLS_SHA1_SOFTWARE, /* using software SHA */
} esp_mbedtls_sha1_mode;
typedef esp_sha_context mbedtls_sha1_context;
/**
* \brief SHA-1 context structure
*/
typedef struct
{
uint32_t total[2]; /*!< number of bytes processed */
uint32_t state[5]; /*!< intermediate digest state */
unsigned char buffer[64]; /*!< data block being processed */
esp_mbedtls_sha1_mode mode;
}
mbedtls_sha1_context;
#define mbedtls_sha1_init esp_sha1_init
#define mbedtls_sha1_starts esp_sha1_start
#define mbedtls_sha1_clone esp_sha1_clone
#define mbedtls_sha1_update esp_sha1_update
#define mbedtls_sha1_finish esp_sha1_finish
#define mbedtls_sha1_free esp_sha1_free
#define mbedtls_sha1_process(...)
/**
* \brief Initialize SHA-1 context
*
* \param ctx SHA-1 context to be initialized
*/
void mbedtls_sha1_init( mbedtls_sha1_context *ctx );
/**
* \brief Clear SHA-1 context
*
* \param ctx SHA-1 context to be cleared
*/
void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
/**
* \brief Clone (the state of) a SHA-1 context
*
* \param dst The destination context
* \param src The context to be cloned
*/
void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
const mbedtls_sha1_context *src );
/**
* \brief SHA-1 context setup
*
* \param ctx context to be initialized
*/
void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
/**
* \brief SHA-1 process buffer
*
* \param ctx SHA-1 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void mbedtls_sha1_update( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen );
/**
* \brief SHA-1 final digest
*
* \param ctx SHA-1 context
* \param output SHA-1 checksum result
*/
void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, unsigned char output[20] );
/* Internal use */
void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] );
#endif

112
tools/sdk/include/mbedtls/sha256_alt.h
View File

@ -1,16 +1,25 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SHA-256 implementation with hardware ESP32 support added.
* Uses mbedTLS software implementation for failover when concurrent
* SHA operations are in use.
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE LTD
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef _SHA256_ALT_H_
#define _SHA256_ALT_H_
@ -20,17 +29,76 @@ extern "C" {
#if defined(MBEDTLS_SHA256_ALT)
#include "hwcrypto/sha.h"
typedef enum {
ESP_MBEDTLS_SHA256_UNUSED, /* first block hasn't been processed yet */
ESP_MBEDTLS_SHA256_HARDWARE, /* using hardware SHA engine */
ESP_MBEDTLS_SHA256_SOFTWARE, /* using software SHA */
} esp_mbedtls_sha256_mode;
typedef esp_sha_context mbedtls_sha256_context;
/**
* \brief SHA-256 context structure
*/
typedef struct
{
uint32_t total[2]; /*!< number of bytes processed */
uint32_t state[8]; /*!< intermediate digest state */
unsigned char buffer[64]; /*!< data block being processed */
int is224; /*!< 0 => SHA-256, else SHA-224 */
esp_mbedtls_sha256_mode mode;
}
mbedtls_sha256_context;
#define mbedtls_sha256_init esp_sha256_init
#define mbedtls_sha256_clone esp_sha256_clone
#define mbedtls_sha256_starts esp_sha256_start
#define mbedtls_sha256_update esp_sha256_update
#define mbedtls_sha256_finish esp_sha256_finish
#define mbedtls_sha256_free esp_sha256_free
#define mbedtls_sha256_process(...)
/**
* \brief Initialize SHA-256 context
*
* \param ctx SHA-256 context to be initialized
*/
void mbedtls_sha256_init( mbedtls_sha256_context *ctx );
/**
* \brief Clear SHA-256 context
*
* \param ctx SHA-256 context to be cleared
*/
void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
/**
* \brief Clone (the state of) a SHA-256 context
*
* \param dst The destination context
* \param src The context to be cloned
*/
void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
const mbedtls_sha256_context *src );
/**
* \brief SHA-256 context setup
*
* \param ctx context to be initialized
* \param is224 0 = use SHA256, 1 = use SHA224
*/
void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 );
/**
* \brief SHA-256 process buffer
*
* \param ctx SHA-256 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input,
size_t ilen );
/**
* \brief SHA-256 final digest
*
* \param ctx SHA-256 context
* \param output SHA-224/256 checksum result
*/
void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, unsigned char output[32] );
/* Internal use */
void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] );
#endif

113
tools/sdk/include/mbedtls/sha512_alt.h
View File

@ -1,16 +1,25 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SHA-512 implementation with hardware ESP32 support added.
* Uses mbedTLS software implementation for failover when concurrent
* SHA operations are in use.
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE LTD
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef _SHA512_ALT_H_
#define _SHA512_ALT_H_
@ -19,17 +28,77 @@ extern "C" {
#endif
#if defined(MBEDTLS_SHA512_ALT)
#include "hwcrypto/sha.h"
typedef esp_sha_context mbedtls_sha512_context;
typedef enum {
ESP_MBEDTLS_SHA512_UNUSED, /* first block hasn't been processed yet */
ESP_MBEDTLS_SHA512_HARDWARE, /* using hardware SHA engine */
ESP_MBEDTLS_SHA512_SOFTWARE, /* using software SHA */
} esp_mbedtls_sha512_mode;
#define mbedtls_sha512_init esp_sha512_init
#define mbedtls_sha512_clone esp_sha512_clone
#define mbedtls_sha512_starts esp_sha512_start
#define mbedtls_sha512_update esp_sha512_update
#define mbedtls_sha512_finish esp_sha512_finish
#define mbedtls_sha512_free esp_sha512_free
#define mbedtls_sha512_process(...)
/**
* \brief SHA-512 context structure
*/
typedef struct
{
uint64_t total[2]; /*!< number of bytes processed */
uint64_t state[8]; /*!< intermediate digest state */
unsigned char buffer[128]; /*!< data block being processed */
int is384; /*!< 0 => SHA-512, else SHA-384 */
esp_mbedtls_sha512_mode mode;
}
mbedtls_sha512_context;
/**
* \brief Initialize SHA-512 context
*
* \param ctx SHA-512 context to be initialized
*/
void mbedtls_sha512_init( mbedtls_sha512_context *ctx );
/**
* \brief Clear SHA-512 context
*
* \param ctx SHA-512 context to be cleared
*/
void mbedtls_sha512_free( mbedtls_sha512_context *ctx );
/**
* \brief Clone (the state of) a SHA-512 context
*
* \param dst The destination context
* \param src The context to be cloned
*/
void mbedtls_sha512_clone( mbedtls_sha512_context *dst,
const mbedtls_sha512_context *src );
/**
* \brief SHA-512 context setup
*
* \param ctx context to be initialized
* \param is384 0 = use SHA512, 1 = use SHA384
*/
void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, int is384 );
/**
* \brief SHA-512 process buffer
*
* \param ctx SHA-512 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void mbedtls_sha512_update( mbedtls_sha512_context *ctx, const unsigned char *input,
size_t ilen );
/**
* \brief SHA-512 final digest
*
* \param ctx SHA-512 context
* \param output SHA-384/512 checksum result
*/
void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, unsigned char output[64] );
/* Internal use */
void mbedtls_sha512_process( mbedtls_sha512_context *ctx, const unsigned char data[128] );
#endif

26
tools/sdk/include/tcpip_adapter/tcpip_adapter.h
View File

@ -98,6 +98,7 @@ typedef struct {
typedef enum {
TCPIP_ADAPTER_IF_STA = 0, /**< ESP32 station interface */
TCPIP_ADAPTER_IF_AP, /**< ESP32 soft-AP interface */
TCPIP_ADAPTER_IF_ETH, /**< ESP32 ethernet interface */
TCPIP_ADAPTER_IF_MAX
} tcpip_adapter_if_t;
@ -354,6 +355,10 @@ esp_err_t tcpip_adapter_dhcpc_start(tcpip_adapter_if_t tcpip_if);
*/
esp_err_t tcpip_adapter_dhcpc_stop(tcpip_adapter_if_t tcpip_if);
esp_err_t tcpip_adapter_eth_input(void *buffer, uint16_t len, void *eb);
/**
* @brief Get data from station interface
*
@ -387,11 +392,12 @@ esp_err_t tcpip_adapter_ap_input(void *buffer, uint16_t len, void *eb);
*
* @param[in] void *dev: adapter interface
*
* @return WIFI_IF_STA
* WIFI_IF_AP
* WIFI_IF_MAX
* @return ESP_IF_WIFI_STA
* ESP_IF_WIFI_AP
ESP_IF_ETH
* ESP_IF_MAX
*/
wifi_interface_t tcpip_adapter_get_wifi_if(void *dev);
esp_interface_t tcpip_adapter_get_esp_if(void *dev);
/**
* @brief Get the station information list
@ -418,6 +424,18 @@ esp_err_t tcpip_adapter_get_sta_list(wifi_sta_list_t *wifi_sta_list, tcpip_adapt
*/
esp_err_t tcpip_adapter_set_hostname(tcpip_adapter_if_t tcpip_if, const char *hostname);
/**
* @brief Get the hostname from the interface
*
* @param[in] tcpip_if: the interface which we will get the hostname
* @param[in] hostname: the host name from the interfce
*
* @return ESP_OK:success
* ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY:interface status error
* ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS:parameter error
*/
esp_err_t tcpip_adapter_get_hostname(tcpip_adapter_if_t tcpip_if, const char **hostname);
#ifdef __cplusplus
}
#endif

60
tools/sdk/include/wpa_supplicant/crypto/ms_funcs.h Normal file
View File

@ -0,0 +1,60 @@
/*
* WPA Supplicant / shared MSCHAPV2 helper functions
*
*
*/
#ifndef MS_FUNCS_H
#define MS_FUNCS_H
int generate_nt_response(const u8 *auth_challenge, const u8 *peer_challenge,
const u8 *username, size_t username_len,
const u8 *password, size_t password_len,
u8 *response);
int generate_nt_response_pwhash(const u8 *auth_challenge,
const u8 *peer_challenge,
const u8 *username, size_t username_len,
const u8 *password_hash,
u8 *response);
int generate_authenticator_response(const u8 *password, size_t password_len,
const u8 *peer_challenge,
const u8 *auth_challenge,
const u8 *username, size_t username_len,
const u8 *nt_response, u8 *response);
int generate_authenticator_response_pwhash(
const u8 *password_hash,
const u8 *peer_challenge, const u8 *auth_challenge,
const u8 *username, size_t username_len,
const u8 *nt_response, u8 *response);
int nt_challenge_response(const u8 *challenge, const u8 *password,
size_t password_len, u8 *response);
void challenge_response(const u8 *challenge, const u8 *password_hash,
u8 *response);
int nt_password_hash(const u8 *password, size_t password_len,
u8 *password_hash);
int hash_nt_password_hash(const u8 *password_hash, u8 *password_hash_hash);
int get_master_key(const u8 *password_hash_hash, const u8 *nt_response,
u8 *master_key);
int get_asymetric_start_key(const u8 *master_key, u8 *session_key,
size_t session_key_len, int is_send,
int is_server);
int encrypt_pw_block_with_password_hash(
const u8 *password, size_t password_len,
const u8 *password_hash, u8 *pw_block);
int __must_check encry_pw_block_with_password_hash(
const u8 *password, size_t password_len,
const u8 *password_hash, u8 *pw_block);
int __must_check new_password_encrypted_with_old_nt_password_hash(
const u8 *new_password, size_t new_password_len,
const u8 *old_password, size_t old_password_len,
u8 *encrypted_pw_block);
void nt_password_hash_encrypted_with_block(const u8 *password_hash,
const u8 *block, u8 *cypher);
int old_nt_password_hash_encrypted_with_new_nt_password_hash(
const u8 *new_password, size_t new_password_len,
const u8 *old_password, size_t old_password_len,
u8 *encrypted_password_hash);
#endif /* MS_FUNCS_H */

13
tools/sdk/include/wpa_supplicant/wpa/common.h
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@ -19,6 +19,19 @@
#endif /* ets */
#include "os.h"
/* Define platform specific variable type macros */
#if defined(ESP_PLATFORM)
#include <stdint.h>
typedef uint64_t u64;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef int64_t s64;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
#endif /*ESP_PLATFORM*/
#if defined(__XTENSA__)
#include <machine/endian.h>
#define __BYTE_ORDER BYTE_ORDER

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