TFT_eSPI/Processors/pio_SPI.pio.h
Bodmer 8a2398451b RP2040: add SPI PIO interface option, enhance 8 bit parallel PIO
The RP2040 processors can now drive 8 bit parallel and SPI displays using the PIO hardware.

The PIO offloads the processor by providing:
1. PIO managed setWindow sequence
2. PIO managed block and screen fill
2022-01-02 01:08:22 +00:00

74 lines
2.7 KiB
C

// -------------------------------------------------- //
// This file is autogenerated by pioasm; do not edit! //
// -------------------------------------------------- //
#pragma once
#if !PICO_NO_HARDWARE
#include "hardware/pio.h"
#endif
// ------ //
// tft_io //
// ------ //
#define tft_io_wrap_target 28
#define tft_io_wrap 31
#define tft_io_offset_start_8 0u
#define tft_io_offset_set_addr_window 5u
#define tft_io_offset_block_fill 18u
#define tft_io_offset_start_16 28u
static const uint16_t tft_io_program_instructions[] = {
0x90a0, // 0: pull block side 0
0x6078, // 1: out null, 24
0x7001, // 2: out pins, 1 side 0
0x18e2, // 3: jmp !osre, 2 side 1
0x101c, // 4: jmp 28 side 0
0xf022, // 5: set x, 2 side 0
0xe000, // 6: set pins, 0
0x90a0, // 7: pull block side 0
0x6078, // 8: out null, 24
0x7001, // 9: out pins, 1 side 0
0x18e9, // 10: jmp !osre, 9 side 1
0xf001, // 11: set pins, 1 side 0
0x003c, // 12: jmp !x, 28
0x80a0, // 13: pull block
0x7001, // 14: out pins, 1 side 0
0x18ee, // 15: jmp !osre, 14 side 1
0x1046, // 16: jmp x--, 6 side 0
0x001c, // 17: jmp 28
0x90a0, // 18: pull block side 0
0xa027, // 19: mov x, osr
0x80a0, // 20: pull block
0xa047, // 21: mov y, osr
0xb0e1, // 22: mov osr, x side 0
0x7011, // 23: out pins, 17 side 0
0xb842, // 24: nop side 1
0x7001, // 25: out pins, 1 side 0
0x18f9, // 26: jmp !osre, 25 side 1
0x1096, // 27: jmp y--, 22 side 0
// .wrap_target
0x90a0, // 28: pull block side 0
0x6070, // 29: out null, 16
0x7001, // 30: out pins, 1 side 0
0x18fe, // 31: jmp !osre, 30 side 1
// .wrap
};
#if !PICO_NO_HARDWARE
static const struct pio_program tft_io_program = {
.instructions = tft_io_program_instructions,
.length = 32,
.origin = -1,
};
static inline pio_sm_config tft_io_program_get_default_config(uint offset) {
pio_sm_config c = pio_get_default_sm_config();
sm_config_set_wrap(&c, offset + tft_io_wrap_target, offset + tft_io_wrap);
sm_config_set_sideset(&c, 2, true, false);
return c;
}
#endif