mirror of
https://github.com/Bodmer/TFT_eSPI.git
synced 2024-09-21 18:37:11 +00:00
parent
c11ecd6932
commit
4cc57699fa
@ -414,21 +414,22 @@
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#if defined (SSD1963_DRIVER)
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// Write 18 bit color to TFT (untested)
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#define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \
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GPIOA->BSRR = D0_BSR_MASK(r) | D2_BSR_MASK(r) | D7_BSR_MASK(r); \
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uint8_t r6, g6, b6;
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#define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \
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GPIOA->BSRR = D0_BSR_MASK(r6) | D2_BSR_MASK(r6) | D7_BSR_MASK(r6); \
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WR_L; \
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GPIOC->BSRR = D1_BSR_MASK(r); \
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GPIOB->BSRR = D3_BSR_MASK(r) | D4_BSR_MASK(r) | D5_BSR_MASK(r) | D6_BSR_MASK(r); \
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GPIOC->BSRR = D1_BSR_MASK(r6); \
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GPIOB->BSRR = D3_BSR_MASK(r6) | D4_BSR_MASK(r6) | D5_BSR_MASK(r6) | D6_BSR_MASK(r6); \
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WR_STB; \
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GPIOA->BSRR = D0_BSR_MASK(g) | D2_BSR_MASK(g) | D7_BSR_MASK(g); \
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GPIOA->BSRR = D0_BSR_MASK(g6) | D2_BSR_MASK(g6) | D7_BSR_MASK(g6); \
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WR_L; \
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GPIOC->BSRR = D1_BSR_MASK(g); \
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GPIOB->BSRR = D3_BSR_MASK(g) | D4_BSR_MASK(g) | D5_BSR_MASK(g) | D6_BSR_MASK(g); \
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GPIOC->BSRR = D1_BSR_MASK(g6); \
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GPIOB->BSRR = D3_BSR_MASK(g6) | D4_BSR_MASK(g6) | D5_BSR_MASK(g6) | D6_BSR_MASK(g6); \
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WR_STB; \
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GPIOA->BSRR = D0_BSR_MASK(b) | D2_BSR_MASK(b) | D7_BSR_MASK(b); \
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GPIOA->BSRR = D0_BSR_MASK(b6) | D2_BSR_MASK(b6) | D7_BSR_MASK(b6); \
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WR_L; \
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GPIOC->BSRR = D1_BSR_MASK(b); \
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GPIOB->BSRR = D3_BSR_MASK(b) | D4_BSR_MASK(b) | D5_BSR_MASK(b) | D6_BSR_MASK(b); \
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GPIOC->BSRR = D1_BSR_MASK(b6); \
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GPIOB->BSRR = D3_BSR_MASK(b6) | D4_BSR_MASK(b6) | D5_BSR_MASK(b6) | D6_BSR_MASK(b6); \
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WR_STB // Need to slow down strobe
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// 18 bit color write with swapped bytes
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@ -556,21 +557,22 @@
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#if defined (SSD1963_DRIVER)
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// Write 18 bit color to TFT (untested)
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#define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \
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GPIOF->BSRR = D0_BSR_MASK(r) | D2_BSR_MASK(r) | D4_BSR_MASK(r) | D7_BSR_MASK(r); \
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uint8_t r6, g6, b6;
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#define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \
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GPIOF->BSRR = D0_BSR_MASK(r6) | D2_BSR_MASK(r6) | D4_BSR_MASK(r6) | D7_BSR_MASK(r6); \
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WR_L; \
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GPIOD->BSRR = D1_BSR_MASK(r); \
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GPIOE->BSRR = D3_BSR_MASK(r) | D5_BSR_MASK(r) | D6_BSR_MASK(r); \
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GPIOD->BSRR = D1_BSR_MASK(r6); \
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GPIOE->BSRR = D3_BSR_MASK(r6) | D5_BSR_MASK(r6) | D6_BSR_MASK(r6); \
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WR_STB; \
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GPIOF->BSRR = D0_BSR_MASK(g) | D2_BSR_MASK(g) | D4_BSR_MASK(g) | D7_BSR_MASK(g); \
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GPIOF->BSRR = D0_BSR_MASK(g6) | D2_BSR_MASK(g6) | D4_BSR_MASK(g6) | D7_BSR_MASK(g6); \
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WR_L; \
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GPIOD->BSRR = D1_BSR_MASK(g); \
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GPIOE->BSRR = D3_BSR_MASK(g) | D5_BSR_MASK(g) | D6_BSR_MASK(g); \
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GPIOD->BSRR = D1_BSR_MASK(g6); \
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GPIOE->BSRR = D3_BSR_MASK(g6) | D5_BSR_MASK(g6) | D6_BSR_MASK(g6); \
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WR_STB; \
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GPIOF->BSRR = D0_BSR_MASK(b) | D2_BSR_MASK(b) | D4_BSR_MASK(b) | D7_BSR_MASK(b); \
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GPIOF->BSRR = D0_BSR_MASK(b6) | D2_BSR_MASK(b6) | D4_BSR_MASK(b6) | D7_BSR_MASK(b6); \
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WR_L; \
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GPIOD->BSRR = D1_BSR_MASK(b); \
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GPIOE->BSRR = D3_BSR_MASK(b) | D5_BSR_MASK(b) | D6_BSR_MASK(b); \
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GPIOD->BSRR = D1_BSR_MASK(b6); \
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GPIOE->BSRR = D3_BSR_MASK(b6) | D5_BSR_MASK(b6) | D6_BSR_MASK(b6); \
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WR_STB // Need to slow down strobe
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// 18 bit color write with swapped bytes
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@ -729,10 +731,11 @@
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#if defined (SSD1963_DRIVER)
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// Write 18 bit color to TFT (untested)
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#define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \
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GPIOA->BSRR = (0x00FF0000 | (uint8_t)(r)); WR_L; WR_STB; \
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GPIOA->BSRR = (0x00FF0000 | (uint8_t)(g)); WR_L; WR_STB; \
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GPIOA->BSRR = (0x00FF0000 | (uint8_t)(b)); WR_L; WR_STB
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uint8_t r6, g6, b6;
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#define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \
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GPIOA->BSRR = (0x00FF0000 | (uint8_t)(r6)); WR_L; WR_STB; \
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GPIOA->BSRR = (0x00FF0000 | (uint8_t)(g6)); WR_L; WR_STB; \
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GPIOA->BSRR = (0x00FF0000 | (uint8_t)(b6)); WR_L; WR_STB
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// 18 bit color write with swapped bytes
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#define tft_Write_16S(C) uint16_t Cswap = ((C) >>8 | (C) << 8); tft_Write_16(Cswap)
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@ -772,10 +775,11 @@
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#if defined (SSD1963_DRIVER)
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// Write 18 bit color to TFT (untested)
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uint8_t r, g, b;
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#define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \
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GPIOB->BSRR = (0x00FF0000 | (uint8_t)(r)); WR_L; WR_STB; \
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GPIOB->BSRR = (0x00FF0000 | (uint8_t)(g)); WR_L; WR_STB; \
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GPIOB->BSRR = (0x00FF0000 | (uint8_t)(b)); WR_L; WR_STB
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GPIOB->BSRR = (0x00FF0000 | (uint8_t)(r6)); WR_L; WR_STB; \
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GPIOB->BSRR = (0x00FF0000 | (uint8_t)(g6)); WR_L; WR_STB; \
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GPIOB->BSRR = (0x00FF0000 | (uint8_t)(b6)); WR_L; WR_STB
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// 18 bit color write with swapped bytes
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#define tft_Write_16S(C) uint16_t Cswap = ((C) >>8 | (C) << 8); tft_Write_16(Cswap)
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@ -885,36 +889,37 @@
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#if defined (SSD1963_DRIVER)
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// Write 18 bit color to TFT (untested)
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#define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \
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D0_PIN_PORT->BSRR = D8_BSR_MASK(r); \
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D1_PIN_PORT->BSRR = D9_BSR_MASK(r); \
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D2_PIN_PORT->BSRR = D10_BSR_MASK(r); \
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D3_PIN_PORT->BSRR = D11_BSR_MASK(r); \
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uint8_t r6, g6, b6;
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#define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \
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D0_PIN_PORT->BSRR = D8_BSR_MASK(r6); \
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D1_PIN_PORT->BSRR = D9_BSR_MASK(r6); \
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D2_PIN_PORT->BSRR = D10_BSR_MASK(r6); \
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D3_PIN_PORT->BSRR = D11_BSR_MASK(r6); \
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WR_L; \
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D4_PIN_PORT->BSRR = D12_BSR_MASK(r); \
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D5_PIN_PORT->BSRR = D13_BSR_MASK(r); \
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D6_PIN_PORT->BSRR = D14_BSR_MASK(r); \
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D7_PIN_PORT->BSRR = D15_BSR_MASK(r); \
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D4_PIN_PORT->BSRR = D12_BSR_MASK(r6); \
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D5_PIN_PORT->BSRR = D13_BSR_MASK(r6); \
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D6_PIN_PORT->BSRR = D14_BSR_MASK(r6); \
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D7_PIN_PORT->BSRR = D15_BSR_MASK(r6); \
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WR_STB;\
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D0_PIN_PORT->BSRR = D8_BSR_MASK(g); \
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D1_PIN_PORT->BSRR = D9_BSR_MASK(g); \
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D2_PIN_PORT->BSRR = D10_BSR_MASK(g); \
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D3_PIN_PORT->BSRR = D11_BSR_MASK(g); \
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D0_PIN_PORT->BSRR = D8_BSR_MASK(g6); \
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D1_PIN_PORT->BSRR = D9_BSR_MASK(g6); \
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D2_PIN_PORT->BSRR = D10_BSR_MASK(g6); \
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D3_PIN_PORT->BSRR = D11_BSR_MASK(g6); \
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WR_L; \
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D4_PIN_PORT->BSRR = D12_BSR_MASK(g); \
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D5_PIN_PORT->BSRR = D13_BSR_MASK(g); \
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D6_PIN_PORT->BSRR = D14_BSR_MASK(g); \
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D7_PIN_PORT->BSRR = D15_BSR_MASK(g); \
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D4_PIN_PORT->BSRR = D12_BSR_MASK(g6); \
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D5_PIN_PORT->BSRR = D13_BSR_MASK(g6); \
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D6_PIN_PORT->BSRR = D14_BSR_MASK(g6); \
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D7_PIN_PORT->BSRR = D15_BSR_MASK(g6); \
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WR_STB;\
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D0_PIN_PORT->BSRR = D0_BSR_MASK(b); \
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D1_PIN_PORT->BSRR = D1_BSR_MASK(b); \
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D2_PIN_PORT->BSRR = D2_BSR_MASK(b); \
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D3_PIN_PORT->BSRR = D3_BSR_MASK(b); \
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D0_PIN_PORT->BSRR = D0_BSR_MASK(b6); \
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D1_PIN_PORT->BSRR = D1_BSR_MASK(b6); \
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D2_PIN_PORT->BSRR = D2_BSR_MASK(b6); \
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D3_PIN_PORT->BSRR = D3_BSR_MASK(b6); \
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WR_L; \
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D4_PIN_PORT->BSRR = D4_BSR_MASK(b); \
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D5_PIN_PORT->BSRR = D5_BSR_MASK(b); \
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D6_PIN_PORT->BSRR = D6_BSR_MASK(b); \
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D7_PIN_PORT->BSRR = D7_BSR_MASK(b); \
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D4_PIN_PORT->BSRR = D4_BSR_MASK(b6); \
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D5_PIN_PORT->BSRR = D5_BSR_MASK(b6); \
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D6_PIN_PORT->BSRR = D6_BSR_MASK(b6); \
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D7_PIN_PORT->BSRR = D7_BSR_MASK(b6); \
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WR_STB
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// 18 bit color write with swapped bytes
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