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Add ability to set the RP2040 parallel interface speed
// For RP2040 processor and 8 or 16 bit parallel displays: // The parallel interface write cycle period is derived from a division of the CPU clock // speed so scales with the processor clock. This means that the divider ratio may need // to be increased when overclocking. I may also need to be adjusted dependant on the // display controller type (ILI94341, HX8357C etc). If RP2040_PIO_CLK_DIV is not defined // the library will set default values which may not suit your display. // The display controller data sheet will specify the minimum write cycle period. The // controllers often work reliably for shorter periods, however if the period is too short // the display may not initialise or graphics will become corrupted. // PIO write cycle frequency = (CPU clock/(4 * RP2040_PIO_CLK_DIV)) //#define RP2040_PIO_CLK_DIV 1 // 32ns write cycle at 125MHz CPU clock #define RP2040_PIO_CLK_DIV 2 // 64ns write cycle at 125MHz CPU clock //#define RP2040_PIO_CLK_DIV 3 // 96ns write cycle at 125MHz CPU clock
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@ -82,9 +82,18 @@
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// Different controllers have different minimum write cycle periods, so the PIO clock is changed accordingly
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// The PIO clock is a division of the CPU clock so scales when the processor is overclocked
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// PIO write frequency = (CPU clock/(4 * DIV_UNITS))
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#if defined (TFT_PARALLEL_8_BIT) || defined (TFT_PARALLEL_16_BIT) || defined (RP2040_PIO_SPI)
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#if defined (TFT_PARALLEL_16_BIT)
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// PIO write frequency = (CPU clock/(4 * RP2040_PIO_CLK_DIV))
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// The write cycle periods below assume a 125MHz CPU clock speed
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#if defined (TFT_PARALLEL_8_BIT) || defined (TFT_PARALLEL_16_BIT)
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#if defined (RP2040_PIO_CLK_DIV)
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#if (RP2040_PIO_CLK_DIV > 0)
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#define DIV_UNITS RP2040_PIO_CLK_DIV
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#define DIV_FRACT 0
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#else
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#define DIV_UNITS 3
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#define DIV_FRACT 0
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#endif
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#elif defined (TFT_PARALLEL_16_BIT)
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// Different display drivers have different minimum write cycle times
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#if defined (HX8357C_DRIVER) || defined (SSD1963_DRIVER)
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#define DIV_UNITS 1 // 32ns write cycle time SSD1963, HX8357C (maybe HX8357D?)
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@ -94,14 +103,9 @@
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#define DIV_UNITS 3 // 96ns write cycle time
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#endif
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#define DIV_FRACT 0
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#else // 8 bit parallel mode
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#ifdef ILI9481_DRIVER
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#define DIV_UNITS 1
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#define DIV_FRACT 160 // Note: Fractional values done with clock period dithering
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#else
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#define DIV_UNITS 1
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#define DIV_FRACT 0
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#endif
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#else // 8 bit parallel mode default 64ns write cycle time
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#define DIV_UNITS 2
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#define DIV_FRACT 0 // Note: Fractional values done with clock period dithering
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#endif
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#endif
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@ -138,143 +138,3 @@
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_height = _init_width;
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break;
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}
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// This is the command sequence that rotates the ST7789 driver coordinate frame
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writecommand(TFT_MADCTL);
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rotation = m % 4;
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switch (rotation) {
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case 0: // Portrait
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#ifdef CGRAM_OFFSET
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if (_init_width == 135)
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{
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colstart = 52;
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rowstart = 40;
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}
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else if(_init_height == 280)
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{
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colstart = 0;
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rowstart = 20;
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}
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else if(_init_width == 172)
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{
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colstart = 34;
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rowstart = 0;
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}
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else if(_init_width == 170)
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{
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colstart = 35;
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rowstart = 0;
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}
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else
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{
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colstart = 0;
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rowstart = 0;
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}
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#endif
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writedata(TFT_MAD_COLOR_ORDER);
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_width = _init_width;
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_height = _init_height;
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break;
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case 1: // Landscape (Portrait + 90)
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#ifdef CGRAM_OFFSET
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if (_init_width == 135)
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{
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colstart = 40;
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rowstart = 53;
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}
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else if(_init_height == 280)
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{
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colstart = 20;
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rowstart = 0;
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}
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else if(_init_width == 172)
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{
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colstart = 0;
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rowstart = 34;
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}
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else if(_init_width == 170)
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{
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colstart = 0;
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rowstart = 35;
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}
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else
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{
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colstart = 0;
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rowstart = 0;
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}
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#endif
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writedata(TFT_MAD_MX | TFT_MAD_MV | TFT_MAD_COLOR_ORDER);
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_width = _init_height;
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_height = _init_width;
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break;
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case 2: // Inverter portrait
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#ifdef CGRAM_OFFSET
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if (_init_width == 135)
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{
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colstart = 53;
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rowstart = 40;
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}
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else if(_init_height == 280)
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{
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colstart = 0;
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rowstart = 20;
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}
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else if(_init_width == 172)
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{
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colstart = 34;
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rowstart = 0;
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}
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else if(_init_width == 170)
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{
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colstart = 35;
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rowstart = 0;
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}
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else
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{
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colstart = 0;
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rowstart = 80;
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}
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#endif
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writedata(TFT_MAD_MX | TFT_MAD_MY | TFT_MAD_COLOR_ORDER);
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_width = _init_width;
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_height = _init_height;
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break;
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case 3: // Inverted landscape
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#ifdef CGRAM_OFFSET
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if (_init_width == 135)
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{
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colstart = 40;
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rowstart = 52;
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}
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else if(_init_height == 280)
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{
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colstart = 20;
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rowstart = 0;
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}
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else if(_init_width == 172)
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{
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colstart = 0;
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rowstart = 34;
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}
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else if(_init_width == 170)
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{
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colstart = 0;
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rowstart = 35;
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}
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else
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{
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colstart = 80;
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rowstart = 0;
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}
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#endif
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writedata(TFT_MAD_MV | TFT_MAD_MY | TFT_MAD_COLOR_ORDER);
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_width = _init_height;
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_height = _init_width;
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break;
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}
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@ -103,7 +103,7 @@
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writedata(0x00);
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writedata(0x00);
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writedata(0x00);
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writedata(0xE5); // 239
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writedata(0xEF); // 239
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writecommand(ST7789_RASET); // Row address set
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writedata(0x00);
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14
User_Setup.h
14
User_Setup.h
@ -324,6 +324,20 @@
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// For RP2040 processor and SPI displays, uncomment the following line to use the PIO interface.
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//#define RP2040_PIO_SPI // Leave commented out to use standard RP2040 SPI port interface
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// For RP2040 processor and 8 or 16 bit parallel displays:
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// The parallel interface write cycle period is derived from a division of the CPU clock
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// speed so scales with the processor clock. This means that the divider ratio may need
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// to be increased when overclocking. I may also need to be adjusted dependant on the
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// display controller type (ILI94341, HX8357C etc). If RP2040_PIO_CLK_DIV is not defined
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// the library will set default values which may not suit your display.
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// The display controller data sheet will specify the minimum write cycle period. The
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// controllers often work reliably for shorter periods, however if the period is too short
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// the display may not initialise or graphics will become corrupted.
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// PIO write cycle frequency = (CPU clock/(4 * RP2040_PIO_CLK_DIV))
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//#define RP2040_PIO_CLK_DIV 1 // 32ns write cycle at 125MHz CPU clock
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//#define RP2040_PIO_CLK_DIV 2 // 64ns write cycle at 125MHz CPU clock
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//#define RP2040_PIO_CLK_DIV 3 // 96ns write cycle at 125MHz CPU clock
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// For the RP2040 processor define the SPI port channel used (default 0 if undefined)
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//#define TFT_SPI_PORT 1 // Set to 0 if SPI0 pins are used, or 1 if spi1 pins used
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