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#940 - Extend allowed TFT_WR pin allocation for ESP32

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TFT_WR is 8 bit parallel mode can now be allocated to GPIO >31
Note: allocating a GPIO higher than 31 has a small perfomance impact (~1.23x slower) since signle register write with the data mask cannot be performed.
This commit is contained in:
Bodmer 2021-01-17 12:03:21 +00:00
parent f6ee102619
commit 22c514cce9
1 changed files with 15 additions and 4 deletions
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19
Processors/TFT_eSPI_ESP32.h
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@ -181,8 +181,12 @@
// Define the WR (TFT Write) pin drive code
////////////////////////////////////////////////////////////////////////////////////////
#if defined (TFT_WR)
#if (TFT_WR >= 0)
// TFT_WR, by design, must be in range 0-31 for single register parallel write
#if (TFT_WR >= 32)
// Note: it will be ~1.25x faster if the TFT_WR pin uses a GPIO pin lower than 32
#define WR_L GPIO.out1_w1tc.val = (1 << (TFT_WR - 32))
#define WR_H GPIO.out1_w1ts.val = (1 << (TFT_WR - 32))
#elif (TFT_WR >= 0)
// TFT_WR, for best performance, should be in range 0-31 for single register parallel write
#define WR_L GPIO.out_w1tc = (1 << TFT_WR)
#define WR_H GPIO.out_w1ts = (1 << TFT_WR)
#else
@ -290,8 +294,15 @@
// Mask for the 8 data bits to set pin directions
#define dir_mask ((1 << TFT_D0) | (1 << TFT_D1) | (1 << TFT_D2) | (1 << TFT_D3) | (1 << TFT_D4) | (1 << TFT_D5) | (1 << TFT_D6) | (1 << TFT_D7))
// Data bits and the write line are cleared to 0 in one step
#define clr_mask (dir_mask | (1 << TFT_WR))
#if (TFT_WR >= 32)
// Data bits and the write line are cleared sequentially
#define clr_mask (dir_mask); WR_L
#elif (TFT_WR >= 0)
// Data bits and the write line are cleared to 0 in one step (1.25x faster)
#define clr_mask (dir_mask | (1 << TFT_WR))
#else
#define clr_mask
#endif
// A lookup table is used to set the different bit patterns, this uses 1kByte of RAM
#define set_mask(C) xset_mask[C] // 63fps Sprite rendering test 33% faster, graphicstest only 1.8% faster than shifting in real time